3 research outputs found
Research on high performance LDPC decoder
制度:新 ; 報告番号:甲3272号 ; 学位の種類:博士(工学) ; 授与年月日:2011/3/15 ; 早大学位記番号:新557
The implementation of an LDPC decoder in a Network on Chip environment
The proposed project takes origin from a cooperation initiative named NEWCOM++ among
research groups to develop 3G wireless mobile system. This work, in particular, tries to focuse on
the communication errors arising on a message signal characterized by working under WiMAX
802.16e standard. It will be shown how this last wireless generation protocol needs a specific
flexible instrumentation and why an LDPC error correction code suitable in order to respect the
quality restrictions. A chapter will be dedicated to describe, not from a mathematical point of view,
the LDPC algorithm theory and how it can be graphically represented to better organize the
decodification process.
The main objective of this work is to validate the PHAL-concept when addressing a
complex and computationally intensive design like the LDPC encoder/decoder. The expected results
should be both conceptual; identifying the lacks on the PHAL concept when addressing a real
problem; and second to determine the overhead introduced by PHAL in the implementation of a
LDPC decoder.
The mission is to build a NoC (Network on Chip) able to perform the same task of a general
purpose processor, but in less time and with better efficiency, in terms of component flexibility and
throughput. The single element of the network is a basic processor element (PE) formed by the
union of two separated components: a special purpose processor ASIP, the responsible of the input
data LDPC decoding, and the router component PHAL, checking incoming data packets and
scanning the temporization of tasks execution.
Supported by a specific programming tool, the ASIP has been completely designed, from the
architecture resources to the instruction set, through a language like C. Realized in this SystemC
code and converted in VHDL language, it's been synthesized as to fit onto an FPGA of the Xilinx
Virtex-5 family. Although the main purpose regards the making of an application as flexible as
possible, a WiMAX-orientated LDPC implemented on a FPGA saves space and resources, choosing
the one that best suits the project synthesis. This is because encoders and decoders will have to find
room in the communication tools (e.g. modems) as best as possible.
The whole network scenary has been mounted through a Linux application, acting as a
master element. The entire environment will require the use of VPI libraries and components able to
manage the communication protocols and interfacing mechanisms
The implementation of an LDPC decoder in a Network on Chip environment
The proposed project takes origin from a cooperation initiative named NEWCOM++ among
research groups to develop 3G wireless mobile system. This work, in particular, tries to focuse on
the communication errors arising on a message signal characterized by working under WiMAX
802.16e standard. It will be shown how this last wireless generation protocol needs a specific
flexible instrumentation and why an LDPC error correction code suitable in order to respect the
quality restrictions. A chapter will be dedicated to describe, not from a mathematical point of view,
the LDPC algorithm theory and how it can be graphically represented to better organize the
decodification process.
The main objective of this work is to validate the PHAL-concept when addressing a
complex and computationally intensive design like the LDPC encoder/decoder. The expected results
should be both conceptual; identifying the lacks on the PHAL concept when addressing a real
problem; and second to determine the overhead introduced by PHAL in the implementation of a
LDPC decoder.
The mission is to build a NoC (Network on Chip) able to perform the same task of a general
purpose processor, but in less time and with better efficiency, in terms of component flexibility and
throughput. The single element of the network is a basic processor element (PE) formed by the
union of two separated components: a special purpose processor ASIP, the responsible of the input
data LDPC decoding, and the router component PHAL, checking incoming data packets and
scanning the temporization of tasks execution.
Supported by a specific programming tool, the ASIP has been completely designed, from the
architecture resources to the instruction set, through a language like C. Realized in this SystemC
code and converted in VHDL language, it's been synthesized as to fit onto an FPGA of the Xilinx
Virtex-5 family. Although the main purpose regards the making of an application as flexible as
possible, a WiMAX-orientated LDPC implemented on a FPGA saves space and resources, choosing
the one that best suits the project synthesis. This is because encoders and decoders will have to find
room in the communication tools (e.g. modems) as best as possible.
The whole network scenary has been mounted through a Linux application, acting as a
master element. The entire environment will require the use of VPI libraries and components able to
manage the communication protocols and interfacing mechanisms