Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

Conception d'amplificateurs de puissance reconfigurables en technologie CMOS avancée pour une application 4G LTE

Cette thèse porte sur la conception d amplificateurs de puissance reconfigurables en technologie CMOS avancée pour une application cellulaire de 4ème génération. Dans les systèmes de communication sans fil, le rendement énergétique est un critère primordial qui impacte la durée d utilisation de la batterie. Principalement déterminé par la consommation d énergie du transmetteur, il est plus particulièrement lié à celle de l amplificateur de puissance (PA). Pour les terminaux mobiles de 4ème génération (4G), les techniques de transmission et les modulations utilisées pour atteindre les débits de données visés induisant une dynamique importante du signal à transmettre, l implémentation de techniques d amélioration du rendement autour du PA devient indispensable, afin de le reconfigurer en puissance.Nous avons mis au point dans ce travail de recherche des architectures innovantes utilisant les techniques d amélioration du Power Cell Switching (PCS) et de l Envelope Tracking (ET). Le double objectif visé étant d améliorer significativement le rendement pour les faibles niveaux de puissance et d apporter de la flexibilité par rapport à un PA utilisé seul. Une première architecture utilisant la technique du PCS totalement intégré en technologie CMOS 65nm de STMicroelectronics, mettant en œuvre des transformateurs comme combineurs de puissance, a été réalisée pour valider la fonctionnalité du concept proposé. Puis une deuxième architecture combinant les techniques du PCS et de l ET a été conçue, afin d évaluer les avantages qu apporte la combinaison de ces deux techniques par rapport à un PA fonctionnant seul et à un PA développé utilisant la technique du PCS.This thesis deals with the design of reconfigurable power amplifiers implemented in CMOS technology for 4G LTE application. For the next generation communication systems such as 4G LTE, orthogonal frequency division multiplexing (OFDM) is employed for a wideband communication. Indeed, signal information is encoded both in amplitude and phase domains, which results in a higher peak to average power ratio than for 2G and 3G systems. Consequently, the overall power amplifier (PA) efficiency does not only depend on efficiency at maximum power, but also and mainly on efficiency at back-off level where the PA operates most of the time. Obviously, classical PA architectures do not address this problem, because it can only achieve maximum efficiency at a single power level, usually around the peak output power. Therefore, the overall efficiency of the PA is considerably low and efficiency improvement techniques are required to increase the battery life-time. This thesis exposes innovative architectures using Power Cell Switching (PCS) and Envelope Tracking (ET) techniques. The main objective of the proposed architectures is to significantly improve the average efficiency in comparison with a stand-alone power amplifier at power back-off. Consequently, a reconfigurable PA architecture using a 4-step PCS technique has been implemented in CMOS 65nm technology. A second architecture was designed to evaluate the improvement obtained with the combination of these two techniques.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF

Analysis and Design of CMOS Radio-Frequency Power Amplifiers

The continuous advancement of semiconductor technologies, especially CMOS technology, has enabled exponential growth of the wireless communication industry. This explosive growth in turn has completely changed people’s lives. The CMOS feature size scale down greatly benefits digital logic integrations, which result in more powerful, versatile, and economical digital signal processing. Further research and development has pushed analog, mixed-signal, and even radio-frequency (RF) circuit blocks to be implemented and integrated in CMOS. Future generations of wireless communication call for even further level of integration, and as of now, the only circuit block that is rarely integrated in CMOS along with other parts of the system is the power amplifier (PA). Due to the fact that the PA in a wireless communication system is the most power-hungry circuit block, the integration of RF PA in CMOS would potentially not only save the cost of the wireless communication system real estate, but also reduce power consumption since die-to-die connection loss can be eliminated. RF PA design involves handling large amounts of voltage and current at the radio frequencies, which in the present wireless communication standards are in the range of giga-hertz. Therefore, a good understanding of many aspects related to RF PA design is necessary. Theoretical analysis of the communication system, nonlinear effects of the PA, as well as the impedance matching network is systematically presented. The analysis of the nonlinear effects proposes a formal mathematical description of the multitone nonlinearity, and through its relationship with two-tone test, the proposed PA design methodology would greatly reduce the design time while improving the design accuracy. A thorough analysis of the available architecture and design techniques for efficiency and linearity enhancement of RF PA shows that despite tremendous amounts of research and development into this topic, the fundamental tradeoff between the two still limits the RF PA implementation largely within SiGe, GaAs, and InP technologies. A RF PA for Wideband Code-Division Multiple Access (WCDMA) application standard is proposed, designed, and implemented in CMOS that demonstrates the proposed segmentation technique that resolved the main tradeoff between power efficiency and linearity. The innovative architecture developed in this work is not limited to applications in the WCDMA communication protocol or the CMOS technology, although CMOS implementation would take advantage of the readily available digital resources

Advances in Integrated Circuit Design and Implementation for New Generation of Wireless Transceivers

User’s everyday outgrowing demand for high-data and high performance mobile devices pushes industry and researchers into more sophisticated systems to fulfill those expectations. Besides new modulation techniques and new system designs, significant improvement is required in the transceiver building blocks to handle higher data rates with reasonable power efficiency. In this research the challenges and solution to improve the performance of wireless communication transceivers is addressed. The building block that determines the efficiency and battery life of the entire mobile handset is the power amplifier. Modulations with large peak to average power ratio severely degrade efficiency in the conventional fixed-biased power amplifiers (PAs). To address this challenge, a novel PA is proposed with an adaptive load for the PA to improve efficiency. A nonlinearity cancellation technique is also proposed to improve linearity of the PA to satisfy the EVM and ACLR specifications. Ultra wide-band (UWB) systems are attractive due to their ability for high data rate, and low power consumption. In spite of the limitation assigned by the FCC, the coexistence of UWB and NB systems are still an unsolved challenge. One of the systems that is majorly affected by the UWB signal, is the 802.11a system (5 GHz Wi-Fi). A new analog solution is proposed to minimize the interference level caused by the impulse Radio UWB transmitter to nearby narrowband receivers. An efficient 400 Mpulse/s IR-UWB transmitter is implemented that generates an analog UWB pulse with in-band notch that covers the majority of the UWB spectrum. The challenge in receiver (RX) design is the over increasing out of blockers in applications such as cognitive and software defined radios, which are required to tolerate stronger out-of-band (OB) blockers. A novel RX is proposed with a shunt N-path high-Q filter at the LNA input to attenuate OB-blockers. To further improve the linearity, a novel baseband blocker filtering techniques is proposed. A new TIA has been designed to maintain the good linearity performance for blockers at large frequency offsets. As a result, a +22 dBm IIP3 with 3.5 dB NF is achieved. Another challenge in the RX design is the tough NF and linearity requirements for high performance systems such as carrier aggregation. To improve the NF, an extra gain stage is added after the LNA. An N-path high-Q band-pass filter is employed at the LNA output together with baseband blocker filtering technique to attenuate out-of-band blockers and improve the linearity. A noise-cancellation technique based on the frequency translation has been employed to improve the NF. As a result, a 1.8dB NF with +5 dBm IIP3 is achieved. In addition, a new approach has been proposed to reject out of band blockers in carrier aggregation scenarios. The proposed solution also provides carrier to carrier isolation compared to typical solution for carrier aggregation