22 research outputs found

    A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications

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    This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2nW at 4kS/s and achieves 9.5 ENOB.Ministerio de Economía y Competitividad TEC2012-33634Office of Naval Research (USA) N0001414135

    Mixed-signal quadratic operators for the feature extraction of neural signals

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    This paper presents design principles for reusing charge-redistribution SAR ADCs as digital multipliers. This is illustrated with an 8-b fully-differential rail-to-rail SAR ADC/multiplier, designed in a 180 nm HV CMOS technology. This reconfigurability property can be exploited for the extraction of product-related features in neural signals, such as energy content, or for the discrimination of spikes using the Teager operator.Ministerio de Economía y Competitividad TEC2012-33634Office of Naval Research (USA) N0001414135

    A 4-Wire Interface SoC for Shared Multi- Implant Power Transfer and Full-duplex Communication

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    This paper describes a novel system for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires a single Chest Device be connected to a Brain Implant consisting of multiple identical optrodes that record neural activity and provide closed loop optical stimulation. The interface is integrated within each optrode SoC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100kbps) superimposed on a power carrier. On-chip power management provides an unregulated 5 V DC supply with up to 2.5 mA output current for stimulation, and a regulated 3.3 V with 60 dB PSRR for recording and logic circuits. The circuit has been implemented in a 0.35 μm CMOS technology, occupying 1.4 mm 2 silicon area, and requiring a 62.2 μA average current consumption

    A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring

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    Four-Wire Interface ASIC for a Multi-Implant Link

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    This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical “optrodes” that facilitate a bidirectional neural interface (electrical recording and optical stimulation), and the chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps), which is superimposed on a power carrier. On-chip power management provides an unregulated 5-V dc supply with up to 2.5-mA output current for stimulation, and two regulated voltages (3.3 and 3 V) with 60-dB power supply rejection ratio for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35-μm CMOS technology, occupying a 1.5-mm 2 silicon area, and consumes a quiescent current of 91.2 μA. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead

    Complementary Detection for Hardware Efficient On-site Monitoring of Parkinsonian Progress

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    The progress of Parkinson & #x2019;s disease (PD) in patients is conventionally monitored through follow-up visits. These may be insufficient for clinicians to obtain a good understanding of the occurrence and severity of symptoms in order to adjust therapy to the patients & #x2019; needs. Portable platforms for PD diagnostics can provide in-depth information, thus reducing the frequency of face-to-face visits. This paper describes the first known on-site PD detection and monitoring processor. This is achieved by employing complementary detection which uses a combination of weak k-NN classifiers to produce a classifier with a higher consistency and confidence level than the individual classifiers. Various implementations of the classifier are investigated for trade-offs in terms of area, power and detection performance. Detection performances are validated on an FPGA platform. Achieved accuracy measures were: Matthews correlation coefficient of 0.6162, mean F1-score of 91.38 & #x0025;, and mean classification accuracy of 91.91 & #x0025;. By mapping the implemented designs on a 45 nm CMOS process, the optimal configuration achieved a dynamic power per channel of 2.26 & #x03BC;W and an area per channel of 0.24 mm2

    Extracellular stimulation system for the modification of network parameters in cultured neural networks

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    Este proyecto se centra en el uso de dispositivos de microelectrodos MEAs (Multi Electrode Arrays) de última generación para el estudio y la manipulación de redes neuronales en cultivo. Chips MEA, con 26400 electrodos situados en una superficie de 3.85x2.10mm^2, fueron utilizados para registrar la actividad eléctrica de dos cultivos de neuronas corticales disociadas obtenidas de embriones de rata. En las mismas plataformas MEA, se implementó un protocolo de estimulación en bucle cerrado, de manera que se pudieran enviar pulsos eléctricos de estimulación a determinados electrodos en respues a potenciales de acción detectados en otro electrodo. Uno de los cultivos de neuronas fue sometido al protocolo de estimulación en bucle cerrado mientras que el segundo cultivo fue utilizado como control. Se desarrollaron diferentes métodos con el fin de hacer una caracterización funcional de los cultivos. El análisis funcional de los registros obtenidos en los experimentos indican que la estimulación en bucle cerrado provocó perdidas significativas y generalizadas de actividad y conectividad en la red neuronal en cultivo
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