A two-stage switched-capacitor integrator for high gain inverter-like architectures

A discrete-time, switched capacitor integrator is presented. The integrator is based on a two-stage architecture where the first stage converts the input voltage into a charge that is accumulated into the second stage. The main strength of the proposed circuit is a higher dc gain with respect to previous solutions, making it optimal for low-voltage inverter-like integrators. A further advantage is the fact that, in contrast with existing solutions, the output voltage is valid across the whole clock cycle. Theoretical analysis of the circuit is performed to calculate the dependence of the integrator dc gain and input-referred offset voltage on the corresponding parameters of the constituting amplifiers. Discrete-time simulations are performed to estimate the gain and phase error with respect to an ideal integrator. The results of electrical simulations performed on an inverter-like prototype, designed with the UMC 0.18-μm CMOS process, are presented to show the impact of non-idealities from the amplifiers and switches

Oversampling Successive Approximation Technique for MEMS Differential Capacitive Sensor

This paper proposed an over sampling successive approximation (OSSA) technique to build switched-capacitor capacitance-to-voltage convertor (SC-CVC) for readout circuit of MEMS differential capacitive sensor. The readout circuit employing the OSSA technique has significantly improved resistance to common-mode parasitic capacitance of the input terminal of the readout circuit. In the OSSA readout circuit, there are 5 main non-ideal characteristics: holding error, recovery degradation, increment degradation, rise-edge degradation and charge injection which reduce the accuracy and the settling time of the circuit. These problems are explained in detail and their solutions are given in the paper. The OSSA readout circuit is fabricated in a commercial 0.18um BCD process. To show the improvement evidently, a reported traditional readout circuit is also reproduced and fabricated using the same process. Compared with the traditional readout circuit, the proposed readout circuit reduces the affect of common-mode parasitic capacitance on the accuracy of SC-CVC by more than 23.8 dB, reduces power dissipation by 69.3%, and reduces die area by 50%