Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

Monolithic integrated reflective transceiver in indium phosphide

The work presented in this thesis is about an InP based monolithic integrated reflective transceiver meant for use in future fiber access networks at the user site. The motivation for this research results from the users’ demands for ever-increasing bandwidth at low cost of operation, administration and maintenance. We investigated solutions to these challenges with a network concept using a dynamically reconfigurable optical network topology with a wavelength router and a colorless optical network unit. This work focuses on developing the optical part of the optical network unit, a reflective transceiver. This reflective transceiver consists of three basic components: a tunable wavelength duplexer, a photodetector and a reflective modulator. The tunable wavelength duplexer separates two wavelengths, one for the downstream and one for the upstream signals, and guides them to the photodetector and the reflective modulator. The photodetector detects the downstream data. The reflective modulator modulates the light carrier with the upstream data and reflects it back to the network. The integrated transceiver was realized bymonolithically integrating these components on a common active-passive butt-joint layer stack based on InP technology. This approach not only offers high bandwidth for both downstream data and upstream data, but also lowers the cost of the device and the network operation because of the colorless operation at the user site. The main results obtained within this work are summarized as follows: an efficient and polarization insensitive tunable wavelength duplexer was realized; a new method to fabricate a reflective SOA has been proposed and demonstrated; a high performance waveguide photodetector based on SOA layer stack was successfully fabricated; a low cost photoreceiverwhich includes an InP photodetector and a SiGe amplifier was demonstrated; aworking monolithic integrated reflective transceiver based on InP was successfully realized and demonstrated; two monolithic integrated transceivers aiming for higher bandwidth have been designed and fabricated. In addition, a novel MMI reflector has been proposed and realized with high reflectivity. This work was funded by DutchMinistry of Economic Affairs through the Freeband Project Broadband Photonics Access, the Smartmix projectMemphis and the NRC Photonics

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC

Continuous-time filters are critical components in the implementation of large bandwidth, high frequency, and high resolution continuous-time (CT) sigma-delta (ΣΔ) analog-to-digital converters (ADCs). The loop filter defines the noise-transfer function (NTF) and hence the quantization noise-shaping behavior of the ΣΔ modulator, and becomes the most critical performance determining part in ΣΔ ADC. This thesis work presents the design considerations for the loop filter in low-pass CT ΣΔ ADC with 12-bits resolution in 25MHz bandwidth and low power consumption using 0.18μm CMOS technology. Continuous-time filters are more suitable than discrete-time filters due to relaxed amplifier bandwidth requirements for high frequency ΣΔ ADCs. A fifth-order low-pass filter with cut-off frequency of 25 MHz was designed to meet the dynamic range requirement of the ADC. An active RC topology was chosen for the implementation of the loop filter, which can provide high dynamic range required by the ΣΔ ADC. The design of a summing amplifier and a novel method for adjusting the group delay in the fast path provided by a secondary feedback DAC of the ΣΔ ADC are presented in detail. The ADC was fabricated using Jazz 0.18μm CMOS technology. The implementation issues of OTAs with high-linearity and low-noise performance suitable for the broadband ADC applications are also analyzed in this work. Important design equations pertaining to the linearity and noise performance of the Gm-C biquad filters are presented. A Gm-C biquad with 100MHz center frequency and quality factor 10 was designed as a prototype to confirm with the theoretical design equations. Transistor level circuit implementation of all the analog modules was completed in a standard 0.18μm CMOS process

High Performance Integrated Circuit Blocks for High-IF Wideband Receivers

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

Imperial Users onl