Improving rewiring scheme and its applications on various circuit design problems.

Lo Wing Hang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 60-61).Abstracts in English and Chinese.Abstract --- p.iChapter 1 --- Introduction --- p.1Chapter 2 --- Preliminaries --- p.5Chapter 2.1 --- Backgrounds and Definitions --- p.5Chapter 2.1.1 --- Boolean Network --- p.5Chapter 2.1.2 --- Transitive Fanin and Fanout Cone --- p.6Chapter 2.1.3 --- Controlling and Sensitizing Values --- p.6Chapter 2.1.4 --- Stuck-at Faults and Test Generation --- p.6Chapter 2.1.5 --- Mandatory Assignments --- p.8Chapter 2.2 --- Review of ATPG-based Rewiring --- p.9Chapter 3 --- Improved Single-Pass Rewiring Scheme Using Inconsistent Assignments --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Overview of FIRE --- p.15Chapter 3.3 --- Alternative Wire Identification Method --- p.17Chapter 3.3.1 --- Identifying Candidate Wires --- p.17Chapter 3.3.2 --- Redundancy Test on Candidate Wire --- p.18Chapter 3.4 --- Redundancy Identification Using Inconsistent Assignments --- p.21Chapter 3.5 --- Experimental Results --- p.26Chapter 3.6 --- Conclusions --- p.28Chapter 4 --- Improving Circuit Partitioning With Rewiring Techniques --- p.29Chapter 4.1 --- Introduction --- p.29Chapter 4.2 --- Implementation of Rewiring Schemes --- p.31Chapter 4.3 --- Coupling Partitioning Algorithm With Rewiring Techniques --- p.33Chapter 4.4 --- Experimental Results --- p.37Chapter 4.5 --- Conclusions --- p.43Chapter 5 --- Circuit Logic Level Reduction by Rewiring for FPGA Mapping --- p.45Chapter 5.1 --- Introduction --- p.45Chapter 5.2 --- Overview of the Technology Mapping Problem --- p.47Chapter 5.2.1 --- Problem Formulation --- p.47Chapter 5.2.2 --- FlowMap Algorithm Outline --- p.49Chapter 5.3 --- Logic Level Reduction by Rewiring Transformations --- p.51Chapter 5.4 --- Experimental Results --- p.54Chapter 5.5 --- Conclusions --- p.57Chapter 6 --- Conclusions and Future Works --- p.58Bibliography --- p.6

Efficient alternative wiring techniques and applications.

Sze, Chin Ngai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 80-84) and index.Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiCurriculum Vitae --- p.ivList of Figures --- p.ixList of Tables --- p.xiiChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation and Aims --- p.1Chapter 1.2 --- Contribution --- p.8Chapter 1.3 --- Organization of Dissertation --- p.10Chapter 2 --- Definitions and Notations --- p.11Chapter 3 --- Literature Review --- p.15Chapter 3.1 --- Logic Reconstruction --- p.15Chapter 3.1.1 --- SIS: A System for Sequential and Combinational Logic Synthesis --- p.16Chapter 3.2 --- ATPG-based Alternative Wiring --- p.17Chapter 3.2.1 --- Redundancy Addition and Removal for Logic Optimization --- p.18Chapter 3.2.2 --- Perturb and Simplify Logic Optimization --- p.18Chapter 3.2.3 --- REWIRE --- p.21Chapter 3.2.4 --- Implication-tree Based Alternative Wiring Logic Trans- formation --- p.22Chapter 3.3 --- Graph-based Alternative Wiring --- p.24Chapter 4 --- Implication Based Alternative Wiring Logic Transformation --- p.25Chapter 4.1 --- Source Node Implication --- p.25Chapter 4.1.1 --- Introduction --- p.25Chapter 4.1.2 --- Implication Relationship and Implication-tree --- p.25Chapter 4.1.3 --- Selection of Alternative Wire Based on Implication-tree --- p.29Chapter 4.1.4 --- Implication-tree Based Logic Transformation --- p.32Chapter 4.2 --- Destination Node Implication --- p.35Chapter 4.2.1 --- Introduction --- p.35Chapter 4.2.2 --- Destination Node Relationship --- p.35Chapter 4.2.3 --- Destination Node Implication-tree --- p.39Chapter 4.2.4 --- Selection of Alternative Wire --- p.41Chapter 4.3 --- The Algorithm --- p.43Chapter 4.3.1 --- IB AW Implementation --- p.43Chapter 4.3.2 --- Experimental Results --- p.43Chapter 4.4 --- Conclusion --- p.45Chapter 5 --- Graph Based Alternative Wiring Logic Transformation --- p.47Chapter 5.1 --- Introduction --- p.47Chapter 5.2 --- Notations and Definitions --- p.48Chapter 5.3 --- Alternative Wire Patterns --- p.50Chapter 5.4 --- Construction of Minimal Patterns --- p.54Chapter 5.4.1 --- Minimality of Patterns --- p.54Chapter 5.4.2 --- Minimal Pattern Formation --- p.56Chapter 5.4.3 --- Pattern Extraction --- p.61Chapter 5.5 --- Experimental Results --- p.63Chapter 5.6 --- Conclusion --- p.63Chapter 6 --- Logic Optimization by GBAW --- p.66Chapter 6.1 --- Introduction --- p.66Chapter 6.2 --- Logic Simplification --- p.67Chapter 6.2.1 --- Single-Addition-Multiple-Removal by Pattern Feature . . --- p.67Chapter 6.2.2 --- Single-Addition-Multiple-Removal by Combination of Pat- terns --- p.68Chapter 6.2.3 --- Single-Addition-Single-Removal --- p.70Chapter 6.3 --- Incremental Perturbation Heuristic --- p.71Chapter 6.4 --- GBAW Optimization Algorithm --- p.73Chapter 6.5 --- Experimental Results --- p.73Chapter 6.6 --- Conclusion --- p.76Chapter 7 --- Conclusion --- p.78Bibliography --- p.80Chapter A --- VLSI Design Cycle --- p.85Chapter B --- Alternative Wire Patterns in [WLFOO] --- p.87Chapter B.1 --- 0-local Pattern --- p.87Chapter B.2 --- 1-local Pattern --- p.88Chapter B.3 --- 2-local Pattern --- p.89Chapter B.4 --- Fanout-reconvergent Pattern --- p.90Chapter C --- New Alternative Wire Patterns --- p.91Chapter C.1 --- Pattern Cluster C1 --- p.91Chapter C.1.1 --- NAND-NAND-AND/NAND;AND/NAND --- p.91Chapter C.1.2 --- NOR-NOR-OR/NOR;AND/NAND --- p.92Chapter C.1.3 --- AND-NOR-OR/NOR;OR/NOR --- p.95Chapter C.1.4 --- OR-NAND-AND/NAND;AND/NAND --- p.95Chapter C.2 --- Pattern Cluster C2 --- p.98Chapter C.3 --- Pattern Cluster C3 --- p.99Chapter C.4 --- Pattern Cluster C4 --- p.104Chapter C.5 --- Pattern Cluster C5 --- p.105Glossary --- p.106Index --- p.10

Logic perturbation based circuit partitioning and optimum FPGA switch-box designs.

Cheung Chak Chung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 101-114).Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiVita --- p.vTable of Contents --- p.viList of Figures --- p.xList of Tables --- p.xivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Aims and Contribution --- p.4Chapter 1.3 --- Thesis Overview --- p.5Chapter 2 --- VLSI Design Cycle --- p.6Chapter 2.1 --- Logic Synthesis --- p.7Chapter 2.1.1 --- Logic Minimization --- p.8Chapter 2.1.2 --- Technology Mapping --- p.8Chapter 2.1.3 --- Testability --- p.8Chapter 2.2 --- Physical Design Synthesis --- p.8Chapter 2.2.1 --- Partitioning --- p.9Chapter 2.2.2 --- Floorplanning & Placement --- p.10Chapter 2.2.3 --- Routing --- p.11Chapter 2.2.4 --- "Compaction, Extraction & Verification" --- p.12Chapter 2.2.5 --- Physical Design of FPGAs --- p.12Chapter 3 --- Alternative Wiring --- p.13Chapter 3.1 --- Introduction --- p.13Chapter 3.2 --- Notation and Definitions --- p.15Chapter 3.3 --- Application of Rewiring --- p.17Chapter 3.3.1 --- Logic Optimization --- p.17Chapter 3.3.2 --- Timing Optimization --- p.17Chapter 3.3.3 --- Circuit Partitioning and Routing --- p.18Chapter 3.4 --- Logic Optimization Analysis --- p.19Chapter 3.4.1 --- Global Flow Optimization --- p.19Chapter 3.4.2 --- OBDD Representation --- p.20Chapter 3.4.3 --- Automatic Test Pattern Generation (ATPG) --- p.22Chapter 3.4.4 --- Graph Based Alternative Wiring (GBAW) --- p.23Chapter 3.5 --- Augmented GBAW --- p.26Chapter 3.6 --- Logic Optimization by using GBAW --- p.28Chapter 3.7 --- Conclusions --- p.31Chapter 4 --- Multi-way Partitioning using Rewiring Techniques --- p.33Chapter 4.1 --- Introduction --- p.33Chapter 4.2 --- Circuit Partitioning Algorithm Analysis --- p.38Chapter 4.2.1 --- The Kernighan-Lin (KL) Algorithm --- p.39Chapter 4.2.2 --- The Fiduccia-Mattheyses (FM) Algorithm --- p.42Chapter 4.2.3 --- Geometric Representation Algorithm --- p.46Chapter 4.2.4 --- The Multi-level Partitioning Algorithm --- p.49Chapter 4.2.5 --- Hypergraph METIS - hMETIS --- p.51Chapter 4.3 --- The GBAW Partitioning Algorithm --- p.53Chapter 4.4 --- Experimental Results --- p.56Chapter 4.5 --- Conclusions --- p.58Chapter 5 --- Optimum FPGA Switch-Box Designs - HUSB --- p.62Chapter 5.1 --- Introduction --- p.62Chapter 5.2 --- Background and Definitions --- p.65Chapter 5.2.1 --- Routing Architectures --- p.65Chapter 5.2.2 --- Global Routing --- p.67Chapter 5.2.3 --- Detailed Routing --- p.67Chapter 5.3 --- FPGA Router Comparison --- p.69Chapter 5.3.1 --- CGE --- p.69Chapter 5.3.2 --- SEGA --- p.70Chapter 5.3.3 --- TRACER --- p.71Chapter 5.3.4 --- VPR --- p.72Chapter 5.4 --- Switch Box Design --- p.73Chapter 5.4.1 --- Disjoint type switch box (XC4000-type) --- p.73Chapter 5.4.2 --- Anti-symmetric switch box --- p.74Chapter 5.4.3 --- Universal Switch box --- p.74Chapter 5.4.4 --- Switch box Analysis --- p.75Chapter 5.5 --- Terminology --- p.77Chapter 5.6 --- "Hyper-universal (4, W)-design analysis" --- p.82Chapter 5.6.1 --- "H3 is an optimum (4, 3)-design" --- p.84Chapter 5.6.2 --- "H4 is an optimum (4,4)-design" --- p.88Chapter 5.6.3 --- "Hi is a hyper-universal (4, i)-design for i = 5,6,7" --- p.90Chapter 5.7 --- Experimental Results --- p.92Chapter 5.8 --- Conclusions --- p.95Chapter 6 --- Conclusions --- p.99Chapter 6.1 --- Thesis Summary --- p.99Chapter 6.2 --- Future work --- p.100Chapter 6.2.1 --- Alternative Wiring --- p.100Chapter 6.2.2 --- Partitioning Quality --- p.100Chapter 6.2.3 --- Routing Devices Studies --- p.100Bibliography --- p.101Chapter A --- 5xpl - Berkeley Logic Interchange Format (BLIF) --- p.115Chapter B --- Proof of some 2-local patterns --- p.122Chapter C --- Illustrations of FM algorithm --- p.124Chapter D --- HUSB Structures --- p.127Chapter E --- Primitive minimal 4-way global routing Structures --- p.13