Stochastic RUL calculation enhanced with TDNN-based IGBT failure modeling

Power electronics are widely used in the transport and energy sectors. Hence, the reliability of these power electronic components is critical to reducing the maintenance cost of these assets. It is vital that the health of these components is monitored for increasing the safety and availability of a system. The aim of this paper is to develop a prognostic technique for estimating the remaining useful life (RUL) of power electronic components. There is a need for an efficient prognostic algorithm that is embeddable and able to support on-board real-time decision-making. A time delay neural network (TDNN) is used in the development of failure modes for an insulated gate bipolar transistor (IGBT). Initially, the time delay neural network is constructed from training IGBTs' ageing samples. A stochastic process is performed for the estimation results to compute the probability of the health state during the degradation process. The proposed TDNN fusion with a statistical approach benefits the probability distribution function by improving the accuracy of the results of the TDDN in RUL prediction. The RUL (i.e., mean and confidence bounds) is then calculated from the simulation of the estimated degradation states. The prognostic results are evaluated using root mean square error (RMSE) and relative accuracy (RA) prognostic evaluation metrics

Accelerated Aging System for Prognostics of Power Semiconductor Devices

Prognostics is an engineering discipline that focuses on estimation of the health state of a component and the prediction of its remaining useful life (RUL) before failure. Health state estimation is based on actual conditions and it is fundamental for the prediction of RUL under anticipated future usage. Failure of electronic devices is of great concern as future aircraft will see an increase of electronics to drive and control safety-critical equipment throughout the aircraft. Therefore, development of prognostics solutions for electronics is of key importance. This paper presents an accelerated aging system for gate-controlled power transistors. This system allows for the understanding of the effects of failure mechanisms, and the identification of leading indicators of failure which are essential in the development of physics-based degradation models and RUL prediction. In particular, this system isolates electrical overstress from thermal overstress. Also, this system allows for a precise control of internal temperatures, enabling the exploration of intrinsic failure mechanisms not related to the device packaging. By controlling the temperature within safe operation levels of the device, accelerated aging is induced by electrical overstress only, avoiding the generation of thermal cycles. The temperature is controlled by active thermal-electric units. Several electrical and thermal signals are measured in-situ and recorded for further analysis in the identification of leading indicators of failures. This system, therefore, provides a unique capability in the exploration of different failure mechanisms and the identification of precursors of failure that can be used to provide a health management solution for electronic devices

Dependable Digitally-Assisted Mixed-Signal IPs Based on Integrated Self-Test & Self-Calibration

Heterogeneous SoC devices, including sensors, analogue and mixed-signal front-end circuits and the availability of massive digital processing capability, are being increasingly used in safety-critical applications like in the automotive, medical, and the security arena. Already a significant amount of attention has been paid in literature with respect to the dependability of the digital parts in heterogeneous SoCs. This is in contrast to especially the sensors and front-end mixed-signal electronics; these are however particular sensitive to external influences over time and hence determining their dependability. This paper provides an integrated SoC/IP approach to enhance the dependability. It will give an example of a digitally-assisted mixed-signal front-end IP which is being evaluated under its mission profile of an automotive tyre pressure monitoring system. It will be shown how internal monitoring and digitally-controlled adaptation by using embedded processors can help in terms of improving the dependability of this mixed-signal part under harsh conditions for a long time

Data-driven prognostics based on evolving fuzzy degradation models for power semiconductor devices

The increasing application of power converter systems based on semiconductor devices such as Insulated-Gate Bipolar Transistors (IGBTs) has motivated the investigation of strategies for their prognostics and health management. However, physicsbased degradation modelling for semiconductors is usually complex and depends on uncertain parameters, which motivates the use of data-driven approaches. This paper addresses the problem of data-driven prognostics of IGBTs based on evolving fuzzy models learned from degradation data streams. The model depends on two classes of degradation features: one group of features that are very sensitive to the degradation stages is used as a premise variable of the fuzzy model, and another group that provides good trendability and monotonicity is used for the auto-regressive consequent of the fuzzy model for degradation prediction. This strategy allows obtaining interpretable degradation models, which are improved when more degradation data is obtained from the Unit Under Test (UUT) in real time. Furthermore, the fuzzy-based Remaining Useful Life (RUL) prediction is equipped with an uncertainty quantification mechanism to better aid decisionmakers. The proposed approach is then used for the RUL prediction considering an accelerated aging IGBT dataset from the NASA Ames Research Center.Postprint (published version

Aging Benefits in Nanometer CMOS Designs

This document is the Accepted Manuscript version of the following article: Daniele Rossi, Vasileios Tenentes, Sheng Yang, Saqib Khursheed, and Bashir M. Al-Hashimi, ‘Aging Benefits in Nanometer CMOS Designs’, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64 (3), May 2016. © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.n this brief, we show that bias temperature instability (BTI) aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to subthreshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only one month of operation, which exceeds 78% in ten years. BTI aging benefits for power consumption are also proven with experimental measurements.Peer reviewedFinal Accepted Versio