Strategies for FPGA Implementation of Non-Restoring Square Root Algorithm

This paper presents three strategies to implement non restoring square root algorithm based on FPGA. A new basic building block is called controlled subtract-multiplex (CSM) is introduced in first strategy which use gate level abstraction. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. Second strategy presents the first strategy in register transfer level (RTL) abstraction. In third strategy, a modification for the implementation of conventional non-restoring algorithm is presented which also use RTL abstraction. The all above strategies is implemented in VHDL programming and adopt fully pipelined architecture. The strategies have conducted to implement successfully in FPGA hardware, and each of the strategies is offer an efficient in hardware resource. In generally, the third strategy is superior.DOI:http://dx.doi.org/10.11591/ijece.v4i4.600

Kemahiran boleh pindah dalam kalangan pelajar kejuruteraan di IPTA

Kemahiran boleh pindah didefinisikan sebagai kemahiran yang dimiliki oleh individu yang mempunyai kepelbagaian pengetahuan, nilai-nilai serta kemahiran hidup asas (life skills) yang diperlukan demi mendapatkan dan mengekalkan pekerjaan sedia ada. Kajian berbentuk tinjauan kuantitatif ini bertujuan untuk mengenal pasti persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya dari aspek adaptif, pemikiran kritis dan penyelesaian masalah. Di samping itu, kajian ini juga bertujuan untuk mengenal pasti perbezaan persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan perbezaan terhadap tahap penguasaannya di antara lelaki dan perempuan. Seramai 297 orang pelajar kejuruteraan tahun tiga lepasan matrikulasi Universiti Tun Hussein Onn Malaysia telah terpilih sebagai responden untuk menjawab borang soal selidik. Data dianalisis dengan mencari nilai skor min dan Ujian-t tidak bersandar menggunakan perisian Statistical Package for Social Science (SPSS). Dapatan kajian menunjukkan bahawa persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya berada pada tahap tinggi dengan nilai skor min 4.0864 dan 4.0282. Kajian juga menunjukkan bahawa wujudnya perbezaan yang signifikan dalam skor min persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah antara lelaki dan perempuan dengan nilai t signifikan 0.003. Namun begitu, hasil analisis menunjukkan tiada perbezaan bagi tahap penguasaannya dengan nilai t signifikan 0.327. Secara keseluruhannya, kesedaran yang tinggi akan membantu pelajar untuk menguasai keseluruhan kemahiran dengan sempurna. Ia juga boleh dijadikan panduan bagi pelajar untuk mengenal pasti elemen dan ciri-ciri yang diperlukan oleh majikan pada masa kini

Kemahiran boleh pindah dalam kalangan pelajar kejuruteraan di IPTA

Kemahiran boleh pindah didefinisikan sebagai kemahiran yang dimiliki oleh individu yang mempunyai kepelbagaian pengetahuan, nilai-nilai serta kemahiran hidup asas (life skills) yang diperlukan demi mendapatkan dan mengekalkan pekerjaan sedia ada. Kajian berbentuk tinjauan kuantitatif ini bertujuan untuk mengenal pasti persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya dari aspek adaptif, pemikiran kritis dan penyelesaian masalah. Di samping itu, kajian ini juga bertujuan untuk mengenal pasti perbezaan persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan perbezaan terhadap tahap penguasaannya di antara lelaki dan perempuan. Seramai 297 orang pelajar kejuruteraan tahun tiga lepasan matrikulasi Universiti Tun Hussein Onn Malaysia telah terpilih sebagai responden untuk menjawab borang soal selidik. Data dianalisis dengan mencari nilai skor min dan Ujian-t tidak bersandar menggunakan perisian Statistical Package for Social Science (SPSS). Dapatan kajian menunjukkan bahawa persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah dan tahap penguasaannya berada pada tahap tinggi dengan nilai skor min 4.0864 dan 4.0282. Kajian juga menunjukkan bahawa wujudnya perbezaan yang signifikan dalam skor min persepsi pelajar terhadap tahap kesedaran kepentingan kemahiran boleh pindah antara lelaki dan perempuan dengan nilai t signifikan 0.003. Namun begitu, hasil analisis menunjukkan tiada perbezaan bagi tahap penguasaannya dengan nilai t signifikan 0.327. Secara keseluruhannya, kesedaran yang tinggi akan membantu pelajar untuk menguasai keseluruhan kemahiran dengan sempurna. Ia juga boleh dijadikan panduan bagi pelajar untuk mengenal pasti elemen dan ciri-ciri yang diperlukan oleh majikan pada masa kini

Dynamically Reconfigurable Architectures and Systems for Time-varying Image Constraints (DRASTIC) for Image and Video Compression

In the current information booming era, image and video consumption is ubiquitous. The associated image and video coding operations require significant computing resources for both small-scale computing systems as well as over larger network systems. For different scenarios, power, bitrate and image quality can impose significant time-varying constraints. For example, mobile devices (e.g., phones, tablets, laptops, UAVs) come with significant constraints on energy and power. Similarly, computer networks provide time-varying bandwidth that can depend on signal strength (e.g., wireless networks) or network traffic conditions. Alternatively, the users can impose different constraints on image quality based on their interests. Traditional image and video coding systems have focused on rate-distortion optimization. More recently, distortion measures (e.g., PSNR) are being replaced by more sophisticated image quality metrics. However, these systems are based on fixed hardware configurations that provide limited options over power consumption. The use of dynamic partial reconfiguration with Field Programmable Gate Arrays (FPGAs) provides an opportunity to effectively control dynamic power consumption by jointly considering software-hardware configurations. This dissertation extends traditional rate-distortion optimization to rate-quality-power/energy optimization and demonstrates a wide variety of applications in both image and video compression. In each application, a family of Pareto-optimal configurations are developed that allow fine control in the rate-quality-power/energy optimization space. The term Dynamically Reconfiguration Architecture Systems for Time-varying Image Constraints (DRASTIC) is used to describe the derived systems. DRASTIC covers both software-only as well as software-hardware configurations to achieve fine optimization over a set of general modes that include: (i) maximum image quality, (ii) minimum dynamic power/energy, (iii) minimum bitrate, and (iv) typical mode over a set of opposing constraints to guarantee satisfactory performance. In joint software-hardware configurations, DRASTIC provides an effective approach for dynamic power optimization. For software configurations, DRASTIC provides an effective method for energy consumption optimization by controlling processing times. The dissertation provides several applications. First, stochastic methods are given for computing quantization tables that are optimal in the rate-quality space and demonstrated on standard JPEG compression. Second, a DRASTIC implementation of the DCT is used to demonstrate the effectiveness of the approach on motion JPEG. Third, a reconfigurable deblocking filter system is investigated for use in the current H.264/AVC systems. Fourth, the dissertation develops DRASTIC for all 35 intra-prediction modes as well as intra-encoding for the emerging High Efficiency Video Coding standard (HEVC)

Efficient FPGA implementation and power modelling of image and signal processing IP cores

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed

Efficient FPGA implementation and power modelling of image and signal processing IP cores

Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobility, reliability concerns and increased design cost among others. Power dissipation has become one of the most important challenges, particularly for FPGAs. Addressing this problem requires optimisation and awareness at all levels in the design flow. The key achievements of the work presented in this thesis are summarised here. Behavioural level optimisation strategies have been used for implementing matrix product and inner product through the use of mathematical techniques such as Distributed Arithmetic (DA) and its variations including offset binary coding, sparse factorisation and novel vector level transformations. Applications to test the impact of these algorithmic and arithmetic transformations include the fast Hadamard/Walsh transforms and Gaussian mixture models. Complete design space exploration has been performed on these cores, and where appropriate, they have been shown to clearly outperform comparable existing implementations. At the architectural level, strategies such as parallelism, pipelining and systolisation have been successfully applied for the design and optimisation of a number of cores including colour space conversion, finite Radon transform, finite ridgelet transform and circular convolution. A pioneering study into the influence of supply voltage scaling for FPGA based designs, used in conjunction with performance enhancing strategies such as parallelism and pipelining has been performed. Initial results are very promising and indicated significant potential for future research in this area. A key contribution of this work includes the development of a novel high level power macromodelling technique for design space exploration and characterisation of custom IP cores for FPGAs, called Functional Level Power Analysis and Modelling (FLPAM). FLPAM is scalable, platform independent and compares favourably with existing approaches. A hybrid, top-down design flow paradigm integrating FLPAM with commercially available design tools for systematic optimisation of IP cores has also been developed.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

PIRANHA: an engine for a methodology of detecting covert communication via image-based steganography

In current cutting-edge steganalysis research, model-building and machine learning has been utilized to detect steganography. However, these models are computationally and cognitively cumbersome, and are specifically and exactly targeted to attack one and only one type of steganography. The model built and utilized in this thesis has shown capability in detecting a class or family of steganography, while also demonstrating that it is viable to construct a minimalist model for steganalysis. The notion of detecting steganographic primitives or families is one that has not been discussed in literature, and would serve well as a first-pass steganographic detection methodology. The model built here serves this end well, and it must be kept in mind that the model presented is posited to work as a front-end broad-pass filter for some of the more computationally advanced and directed stganalytic algorithms currently in use. This thesis attempts to convey a view of steganography and steganalysis in a manner more utilitarian and immediately useful to everyday scenarios. This is vastly different from a good many publications that treat the topic as one relegated only to cloak-and-dagger information passing. The subsequent view of steganography as primarily a communications tool useable by petty information brokers and the like directs the text and helps ensure that the notion of steganography as a digital dead-drop box is abandoned in favor of a more grounded approach. As such, the model presented underperforms specialized models that have been presented in current literature, but also makes use of a large image sample space (747 images) as well as images that are contextually diverse and representative of those seen in wide use. In future applications by either law-enforcement or corporate officials, it is hoped that the model presented in this thesis can aid in rapid and targeted responses without causing undue strain upon an eventual human operator. As such, a design constraint that was utilized for this research favored a False Negative as opposed to a False Positive - this methodology helps to ensure that, in the event of an alert, it is worthwhile to apply a more directed attack against the flagged image