MicroTCA implementation of synchronous Ethernet-Based DAQ systems for large scale experiments

Large LAr TPCs are among the most powerful detectors to address open problems in particle and astro-particle physics, such as CP violation in leptonic sector, neutrino properties and their astrophysical implications, proton decay search etc. The scale of such detector implies severe constraints on their readout and DAQ system. In this article we describe a data acquisition scheme for this new generation of large detectors. The main challenge is to propose a scalable and easy to use solution able to manage a large number of channels at the lowest cost. It is interesting to note that these constraints are very similar to those existing in Network Telecommunication Industry. We propose to study how emerging technologies like ATCA and $\mu$TCA could be used in neutrino experiments. We describe the design of an Advanced Mezzanine Board (AMC) including 32 ADC channels. This board receives 32 analogical channels at the front panel and sends the formatted data through the $\mu$TCA backplane using a Gigabit Ethernet link. The gigabit switch of the MCH is used to centralize and to send the data to the event building computer. The core of this card is a FPGA (ARIA-GX from ALTERA) including the whole system except the memories. A hardware accelerator has been implemented using a NIOS II $\mu$P and a Gigabit MAC IP. Obviously, in order to be able to reconstruct the tracks from the events a time synchronisation system is mandatory. We decided to implement the IEEE1588 standard also called Precision Timing Protocol, another emerging and promising technology in Telecommunication Industry. In this article we describe a Gigabit PTP implementation using the recovered clock of the gigabit link. By doing so the drift is directly cancelled and the PTP will be used only to evaluate and to correct the offset.Comment: Talk presented at the 2009 Real Time Conference, Beijing, May '09, submitted to the proceeding

FPGA based data acquisition system for COMPASS experiment

This paper discusses the present data acquisition system (DAQ) of the COMPASS experiment at CERN and presents development of a new DAQ. The new DAQ must preserve present data format and be able to communicate with FPGA cards. Parts of the new DAQ are based on state machines and they are implemented in C++ with usage of the QT framework, the DIM library, and the IPBus technology. Prototype of the system is prepared and communication through DIM between parts was tested. An implementation of the IPBus technology was prepared and tested. The new DAQ proved to be able to fulfill requirements.Comment: 8 pages, CHEP 201

Satellite range delay simulator for a matrix-switched time division multiple-access network simulator

The Systems Integration, Test, and Evaluation (SITE) facility at NASA Lewis Research Center is presently configured as a satellite-switched time division multiple access (SS-TDMA) network simulator. The purpose of SITE is to demonstrate and evaluate advanced communication satellite technologies, presently embodied by POC components developed under NASA contracts in addition to other hardware, such as ground terminals, designed and built in-house at NASA Lewis. Each ground terminal in a satellite communications system will experience a different aspect of the satellite's motion due mainly to daily tidal effects and station keeping, hence a different duration and rate of variation in the range delay. As a result of this and other effects such as local oscillator instability, each ground terminal must constantly adjust its transmit burst timing so that data bursts from separate ground terminals arrive at the satellite in their assigned time slots, preventing overlap and keeping the system in synchronism. On the receiving end, ground terminals must synchronize their local clocks using reference transmissions received through the satellite link. A feature of the SITE facility is its capability to simulate the varying propagation delays and associated Doppler frequency shifts that the ground terminals in the network have to cope with. Delay is achieved by means of two NASA Lewis designed and built range delay simulator (RDS) systems, each independently controlled locally with front panel switches or remotely by an experiment control and monitor (EC/M) computer

Digitally modulated bit error rate measurement system for microwave component evaluation

The NASA Lewis Research Center has developed a unique capability for evaluation of the microwave components of a digital communication system. This digitally modulated bit-error-rate (BER) measurement system (DMBERMS) features a continuous data digital BER test set, a data processor, a serial minimum shift keying (SMSK) modem, noise generation, and computer automation. Application of the DMBERMS has provided useful information for the evaluation of existing microwave components and of design goals for future components. The design and applications of this system for digitally modulated BER measurements are discussed

The S2 VLBI Correlator: A Correlator for Space VLBI and Geodetic Signal Processing

We describe the design of a correlator system for ground and space-based VLBI. The correlator contains unique signal processing functions: flexible LO frequency switching for bandwidth synthesis; 1 ms dump intervals, multi-rate digital signal-processing techniques to allow correlation of signals at different sample rates; and a digital filter for very high resolution cross-power spectra. It also includes autocorrelation, tone extraction, pulsar gating, signal-statistics accumulation.Comment: 44 pages, 13 figure