1,874 research outputs found
Parallel discrete event simulation: A shared memory approach
With traditional event list techniques, evaluating a detailed discrete event simulation model can often require hours or even days of computation time. Parallel simulation mimics the interacting servers and queues of a real system by assigning each simulated entity to a processor. By eliminating the event list and maintaining only sufficient synchronization to insure causality, parallel simulation can potentially provide speedups that are linear in the number of processors. A set of shared memory experiments is presented using the Chandy-Misra distributed simulation algorithm to simulate networks of queues. Parameters include queueing network topology and routing probabilities, number of processors, and assignment of network nodes to processors. These experiments show that Chandy-Misra distributed simulation is a questionable alternative to sequential simulation of most queueing network models
SDL based validation of a node monitoring protocol
Mobile ad hoc network is a wireless, self-configured, infrastructureless
network of mobile nodes. The nodes are highly mobile, which makes the
application running on them face network related problems like node failure,
link failure, network level disconnection, scarcity of resources, buffer
degradation, and intermittent disconnection etc. Node failure and Network fault
are need to be monitored continuously by supervising the network status. Node
monitoring protocol is crucial, so it is required to test the protocol
exhaustively to verify and validate the functionality and accuracy of the
designed protocol. This paper presents a validation model for Node Monitoring
Protocol using Specification and Description Llanguage (SDL) using both Static
Agent (SA) and Mobile Agent (MA). We have verified properties of the Node
Monitoring Protocol (NMP) based on the global states with no exits, deadlock
states or proper termination states using reachability graph. Message Sequence
Chart (MSC) gives an intuitive understanding of the described system behavior
with varying node density and complex behavior etc.Comment: 16 pages, 24 figures, International Conference of Networks,
Communications, Wireless and Mobile 201
Design of deadlock detection and prevention algorithms in distributed systems
A distributed system consists of a collection of processes which communicate with each other by exchanging messages to achieve a common goal. One of the key problems in distributed systems is the possibility of deadlock. Processes are said to be deadlocked when some processes are blocked on resource requests that can never be satisfied unless drastic systems action is taken. Two distributed deadlock detection algorithms handling multiple outstanding requests is proposed and are proven to be correct: it detects all cycles and does not detect false deadlocks. The algorithms are based on the concept of chasing the edge of the waitfor graph (probe-based). Simulation results show that the proposed algorithm performs very well compared to some existing algorithms. A deadlock prevention algorithm based on the notion of coloring the nodes of the waitfor graph is also proposed. Rollback is quite less compared to some existing algorithms
UPC-CHECK: A scalable tool for detecting run-time errors in Unified Parallel C
Unied Parallel C (UPC) is a language used to write parallel programs for shared and distributed memory parallel computers. UPC-CHECK is a scalable tool developed to automatically detect argument errors in UPC functions and deadlocks in UPC programs at run-time and issue high quality error messages to help programmers quickly x those errors. The tool is easy to use and involves merely replacing the compiler command with upc-check. The tool uses a novel distributed algorithm for detecting argument and deadlock errors in collective operations. The run-time complexity of the algorithm has been proven to be O(1). The algorithm has been extended to detect deadlocks created involving locks with a run-time complexity of O(T), where T is the number of threads waiting to acquire a lock. Error messages issued by UPC-CHECK were evaluated using the UPC RTED test suite for argument errors
in UPC functions and deadlocks. Results of these tests show that the error messages issued by UPC-CHECK for these tests are excellent. The scalability of all the algorithms used was demonstrated using performance-evaluation test programs and the UPC NAS Parallel Benchmarks
Implementing deadlock detection in distributed processing, 1985
Many protocols have been published on the topic of deadlock detection in distributed processing. A survey has been made on four of these varied schemes. The method of 'distributed locking and distributed deadlock detection protocol' has been selected for implementation. Data structures and various routines for this particular protocol have been fully developed, and the resulting program exhaustively tested. In all test cases, results were positive and based on these results, we believe we have succeeded in implementing a deadlock detecting scheme for distributed processing
Embedded dynamic programming networks for networks-on-chip
PhD ThesisRelentless technology downscaling and recent technological advancements
in three dimensional integrated circuit (3D-IC) provide a promising
prospect to realize heterogeneous system-on-chip (SoC) and homogeneous
chip multiprocessor (CMP) based on the networks-onchip
(NoCs) paradigm with augmented scalability, modularity and
performance. In many cases in such systems, scheduling and managing
communication resources are the major design and implementation
challenges instead of the computing resources. Past research
efforts were mainly focused on complex design-time or simple heuristic
run-time approaches to deal with the on-chip network resource
management with only local or partial information about the network.
This could yield poor communication resource utilizations and amortize
the benefits of the emerging technologies and design methods.
Thus, the provision for efficient run-time resource management in
large-scale on-chip systems becomes critical. This thesis proposes a
design methodology for a novel run-time resource management infrastructure
that can be realized efficiently using a distributed architecture,
which closely couples with the distributed NoC infrastructure. The
proposed infrastructure exploits the global information and status
of the network to optimize and manage the on-chip communication
resources at run-time.
There are four major contributions in this thesis. First, it presents a
novel deadlock detection method that utilizes run-time transitive closure
(TC) computation to discover the existence of deadlock-equivalence
sets, which imply loops of requests in NoCs. This detection scheme,
TC-network, guarantees the discovery of all true-deadlocks without
false alarms in contrast to state-of-the-art approximation and heuristic
approaches. Second, it investigates the advantages of implementing
future on-chip systems using three dimensional (3D) integration and
presents the design, fabrication and testing results of a TC-network
implemented in a fully stacked three-layer 3D architecture using a
through-silicon via (TSV) complementary metal-oxide semiconductor
(CMOS) technology. Testing results demonstrate the effectiveness
of such a TC-network for deadlock detection with minimal computational
delay in a large-scale network. Third, it introduces an adaptive
strategy to effectively diffuse heat throughout the three dimensional
network-on-chip (3D-NoC) geometry. This strategy employs a dynamic
programming technique to select and optimize the direction of data
manoeuvre in NoC. It leads to a tool, which is based on the accurate
HotSpot thermal model and SystemC cycle accurate model, to simulate
the thermal system and evaluate the proposed approach. Fourth, it
presents a new dynamic programming-based run-time thermal management
(DPRTM) system, including reactive and proactive schemes, to
effectively diffuse heat throughout NoC-based CMPs by routing packets
through the coolest paths, when the temperature does not exceed
chip’s thermal limit. When the thermal limit is exceeded, throttling is
employed to mitigate heat in the chip and DPRTM changes its course
to avoid throttled paths and to minimize the impact of throttling on
chip performance.
This thesis enables a new avenue to explore a novel run-time resource
management infrastructure for NoCs, in which new methodologies
and concepts are proposed to enhance the on-chip networks for
future large-scale 3D integration.Iraqi Ministry of Higher Education and Scientific Research (MOHESR)
The combinatorics of resource sharing
We discuss general models of resource-sharing computations, with emphasis on
the combinatorial structures and concepts that underlie the various deadlock
models that have been proposed, the design of algorithms and deadlock-handling
policies, and concurrency issues. These structures are mostly graph-theoretic
in nature, or partially ordered sets for the establishment of priorities among
processes and acquisition orders on resources. We also discuss graph-coloring
concepts as they relate to resource sharing.Comment: R. Correa et alii (eds.), Models for Parallel and Distributed
Computation, pp. 27-52. Kluwer Academic Publishers, Dordrecht, The
Netherlands, 200
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