Parallelization of Fast 1-Minimization for Face Recognition

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryRecently a family of promising face recognition algorithms based on sparse representation and `1-minimization (`1-min) have been developed. These algorithms have not yet seen commercial application, largely due to higher computational cost compared to other traditional algorithms. This paper studies techniques for leveraging the massive parallelism available in GPU and CPU hardware to accelerate `1-min based on augmented Lagrangian method (ALM) solvers. For very large problems, the GPU is faster due to higher memory bandwidth, while for problems that fit in the larger CPU L3 cache, the CPU is faster. On both architectures, the proposed implementations significantly outperform naive library-based implementations, as well as previous systems. The source code of the algorithms will be made available for peer evaluation.ONR / N00014-09-1-023

Accelerated High-Performance Compressive Sensing using the Graphics Processing Unit

This thesis demonstrates the advantages of new practical implementations of compressive sensing (CS) algorithms tailored for the graphics processing unit (CPU) using a software platform called Jacket. There exist many applications which utilize CS including medical imaging, signal processing and data acquisition which have benefited from advancements in CS. However, as problems become larger not only do they become more difficult to solve but also more computationally expensive. In light of tins, existing CS algorithms are augmented for practical use on the CPU, reaping performance gains from the highly parallel architecture of the GPU. I discuss the issues associated with this transition and analyze the effects of such a movement, as well as provide results exhibiting advantages of using CPU-based methods

High-performance and hardware-aware computing: proceedings of the second International Workshop on New Frontiers in High-performance and Hardware-aware Computing (HipHaC\u2711), San Antonio, Texas, USA, February 2011 ; (in conjunction with HPCA-17)

High-performance system architectures are increasingly exploiting heterogeneity. The HipHaC workshop aims at combining new aspects of parallel, heterogeneous, and reconfigurable microprocessor technologies with concepts of high-performance computing and, particularly, numerical solution methods. Compute- and memory-intensive applications can only benefit from the full hardware potential if all features on all levels are taken into account in a holistic approach

A Compressive Sensing Algorithm for Many-Core Architectures

This paper describes a parallel algorithm for solving the l(1)-compressive sensing problem. Its design takes advantage of shared memory, vectorized, parallel and many-core microprocessors such as Graphics Processing Units (GPUs) and standard vectorized multi-core processors (e.g. quad-core CPUs). Experiments are conducted on these architectures, showing evidence of the efficiency of our approach