MCFlow: Middleware for Mixed-Criticality Distributed Real-Time Systems

Traditional fixed-priority scheduling analysis for periodic/sporadic task sets is based on the assumption that all tasks are equally critical to the correct operation of the system. Therefore, every task has to be schedulable under the scheduling policy, and estimates of tasks\u27 worst case execution times must be conservative in case a task runs longer than is usual. To address the significant under-utilization of a system\u27s resources under normal operating conditions that can arise from these assumptions, several \emph{mixed-criticality scheduling} approaches have been proposed. However, to date there has been no quantitative comparison of system schedulability or run-time overhead for the different approaches. In this dissertation, we present what is to our knowledge the first side-by-side implementation and evaluation of those approaches, for periodic and sporadic mixed-criticality tasks on uniprocessor or distributed systems, under a mixed-criticality scheduling model that is common to all these approaches. To make a fair evaluation of mixed-criticality scheduling, we also address some previously open issues and propose modifications to improve schedulability and correctness of particular approaches. To facilitate the development and evaluation of mixed-criticality applications, we have designed and developed a distributed real-time middleware, called MCFlow, for mixed-criticality end-to-end tasks running on multi-core platforms. The research presented in this dissertation provides the following contributions to the state of the art in real-time middleware: (1) an efficient component model through which dependent subtask graphs can be configured flexibly for execution within a single core, across cores of a common host, or spanning multiple hosts; (2) support for optimizations to inter-component communication to reduce data copying without sacrificing the ability to execute subtasks in parallel; (3) a strict separation of timing and functional concerns so that they can be configured independently; (4) an event dispatching architecture that uses lock free algorithms where possible to reduce memory contention, CPU context switching, and priority inversion; and (5) empirical evaluations of MCFlow itself and of different mixed criticality scheduling approaches both with a single host and end-to-end across multiple hosts. The results of our evaluation show that in terms of basic distributed real-time behavior MCFlow performs comparably to the state of the art TAO real-time object request broker when only one core is used and outperforms TAO when multiple cores are involved. We also identify and categorize different use cases under which different mixed criticality scheduling approaches are preferable

RFID User Memory를 통한 생산 관리 및 일정 계획 수립 활용 방안에 대한 연구

학위논문 (석사)-- 서울대학교 대학원 : 산업공학과 산업공학 전공, 2016. 8. 박진우.Industrial products nowadays consist of tens of thousands of parts, and the corresponding supply chains for these products are constituted by large numbers of component suppliers. In these complex supply chains, the use of radio-frequency identification (RFID) can be a viable method to collect real-time shop floor information, including that pertaining to inventory or work progress. However, little to no research to date has been conducted on the use of RFID-based real-time information systems in traditional scheduling problems, although such technologies offer considerable benefit. The RFID tag data standard has recently been developed to set guidelines for the user memory bank for storing or sharing business data on tag user memory. In this study, the thesis propose a real-time response scheduling system that utilizes this new RFID technology. Proposed system include tag based data structure, pre-processing of data and production scheduling algorithm. This research show that quicker response scheduling solutions are available, and verify the efficiency of the proposed solution through a simulation.1. Introduction 1 1.1 Background and motivation 1 1.2 Research objective and scope 3 1.3 Structure of the thesis 5 2. Related work 6 2.1 RFID 6 2.1.1 RFID in industries 7 2.1.2 Electronic Product Code 9 2.1.3 Adoption and application of RFID tag user memory bank 13 2.2 Production scheduling problem 14 2.2.1 Shop floor production scheduling 14 2.2.2 Real-time production scheduling problem 16 3. Problem description 19 3.1 Model framework 20 3.2 Assumptions 21 3.3 Mathematical modeling 21 3.3.1 Parameter and variable 21 3.3.2 Objective function 22 3.3.3 Constraints 23 3.4 Problem and model description 25 4. RFID-based real-time production management and scheduling system 28 4.1 RFID data architecture for production management and scheduling 28 4.2 RFID-based real-time production scheduling algorithm 33 4.2.1 Data pre-processing for scheduling algorithm 33 4.2.2 Modified NEH algorithm 35 4.2.3 Feasibility check 38 5. Case study 39 5.1 Introduction to case study 39 5.2 Simulation description 42 5.3 Evaluation 43 5.4 Results and discussion 44 6. Conclusion and future work 53 6.1 Summary 53 6.2 Limitations and future work 54 Bibliography 55 초록 60Maste

High-level synthesis under I/O Timing and Memory constraints

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm

AADLib, A Library of Reusable AADL Models

The SAE Architecture Analysis and Design Language is now a well-established language for the description of critical embedded systems, but also cyber-physical ones. A wide range of analysis tools is already available, either as part of the OSATE tool chain, or separate ones. A key missing elements of AADL is a set of reusable building blocks to help learning AADL concepts, but also experiment already existing tool chains on validated real-life examples. In this paper, we present AADLib, a library of reusable model elements. AADLib is build on two pillars: 1/ a set of ready-to- use examples so that practitioners can learn more about the AADL language itself, but also experiment with existing tools. Each example comes with a full description of available analysis and expected results. This helps reducing the learning curve of the language. 2/ a set of reusable model elements that cover typical building blocks of critical systems: processors, networks, devices with a high level of fidelity so that the cost to start a new project is reduced. AADLib is distributed under a Free/Open Source License to further disseminate the AADL language. As such, AADLib provides a convenient way to discover AADL concepts and tool chains, and learn about its features