An Automated Design-flow for FPGA-based Sequential Simulation

In this paper we describe the automated design flow that will transform and map a given homogeneous or heterogeneous hardware design into an FPGA that performs a cycle accurate simulation. The flow replaces the required manually performed transformation and can be embedded in existing standard synthesis flows. Compared to the earlier manually translated designs, this automated flow resulted in a reduced number of FPGA hardware resources and higher simulation frequencies. The implementation of the complete design flow is work in progress.\u

Fast, Accurate and Detailed NoC Simulations

Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router's RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a speed-up of 80-300, without compromising the cycle and bit level accuracy

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System

Heracles is an open-source complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies and sizes. Each processing node has a 7-stage pipeline, fully bypassed, microprocessor running the MIPS-III ISA, a 4-stage input-buffer, virtual-channel router, and a local variable-size shared memory. Our design is highly modular with clear interfaces between the core, the memory hierarchy, and the on-chip network. In the baseline design, the microprocessor is attached to two caches, one instruction cache and one data cache, which are oblivious to the global memory organization. The memory system in Heracles can be configured as one single global shared memory (SM), or distributed shared memory (DSM), or any combination thereof. Each core is connected to the rest of the network of processors by a parameterized, realistic, wormhole router. We show different topology configurations of the system, and their synthesis results on the Xilinx Virtex-5 LX330T FPGA board. We also provide a small MIPS cross-compiler toolchain to assist in developing software for Heracles

Програмна модель мереж на кристалі із нерегулярними топологіями

The review of different approaches to the simulation of the networks-on-chip (NoC) is performed. The simulator of the NoC where the topology is set with the matrix of connections between the routers that manage the traffic by means of the routing tables is developed. The capabilities of the NoC simulator are examined and the results of its approbation by the example of the regular and quasi-optimal NoCs are presentedПроведен обзор различных подходов к моделированию сетей на кристалле (СтнК). Разработан симулятор СтнК, где топология задается матрицей связей между роутерами, которые управляют трафиком с помощью таблиц маршрутизации. Рассмотрены возможности симулятора СтнК и представлены результаты его апробации на примере регулярных и квазиоптимальных сетейПроведено огляд різних підходів до моделювання мереж на кристалі (МнК). Розроблено симулятор МнК, у якому топологія задається матрицею зв’язків між роутерами, що керують трафіком за допомогою таблиць маршрутизації. Розглянуто можливості симулятора МнК та представлені результати його апробації на прикладі регулярних і квазіоптимальних мере

Heracles: A Tool for Fast RTL-Based Design Space Exploration of Multicore Processors

This paper presents Heracles, an open-source, functional, parameterized, synthesizable multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile research and teaching tool for architectural exploration and hardware-software co-design. The Heracles toolkit comprises the soft hardware (HDL) modules, application compiler, and graphical user interface. It is designed with a high degree of modularity to support fast exploration of future multicore processors of di erent topologies, routing schemes, processing elements (cores), and memory system organizations. It is a component-based framework with parameterized interfaces and strong emphasis on module reusability. The compiler toolchain is used to map C or C++ based applications onto the processing units. The GUI allows the user to quickly con gure and launch a system instance for easy factorial development and evaluation. Hardware modules are implemented in synthesizable Verilog and are FPGA platform independent. The Heracles tool is freely available under the open-source MIT license at: http://projects.csail.mit.edu/heracle

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple complex real-time applications (e.g. video processing, or videogames), while meeting several additional design constraints (e.g. energy consumption or time-to-market). Therefore, mechanisms to efficiently explore the different possible HW-SW design interactions in complete MPSoC systems are in great need. In this paper, we present a new FPGA-based emulation framework that allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level. Our results show that the proposed framework is able to extract a number of critical statistics from processing cores, memory and interconnection systems, with a speed-up of three orders of magnitude compared to cycle accurate MPSoC simulators

Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple complex real-time applications (e.g. video processing, or videogames), while meeting several additional design constraints (e.g. energy consumption or time-to-market). Thus, in order to explore all the possible HW-SW configurations in a MPSoC, simulation is not practical anymore due to the large overhead in time of cycle-accurate simulators, which is the desired level for the extraction of statistics. New methods to extract such fine-grained statistics in a faster way are needed. In this paper, we present a new FPGA-based emulation framework that allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level. Our experimients using this platform yield a speed-up of three orders of magnitud compared to cycle-accurate MPSoC simulators, while achieving the same level of accuracy as cycle-accurate MPSoC simulation frameworks

NoC emulation: a tool and design flow for MPSoC

Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing; thus, the amount of processors, memories and application-specific signal pro- cessing cores is rapidly increasing. In these new Multi- Processor SoCs, (MPSoCs) one of the most critical elements regarding overall efficiency is on-chip interconnections. Network-On-Chip(NoC) provides a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or ad hoc topologies and can be tuned by a large set of parameters. Simulation and functional validation are essential to assess the correctness and performance of MPSoC architectures. We present a flexible hardware-software emulation framework implemented on an FPGA that is specially designed to suitably explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy and flexibility of software simulators. Finally, we propose a validation flow for MPSoCs based on our flexible NoC emulation framework, which allows designers to explore and optimize a range of solutions, as well as quickly characterize performance figures and identify possible limitations in their on-chip interconnection architectures

DiAMOND:Distributed Alteration of Messages for On-Chip Network Debug

Abstract-During emulation and post-silicon validation of networks-on-chip (NoCs), lack of observability of internal operations hinders the detection and debugging of functional bugs. Verifying the correctness of the control-flow portion of the NoC requires tests that exercise its functionality, while abstracting the data content of traffic. We propose a methodology where network packets are repurposed for the storage of debug information collected during execution. Debug data pertaining to each packet is collected at routers along its path and stored by replacing the packet's original data content. Our solution is coupled with a detection scheme consisting of small checkers that monitor execution and flag bugs. Upon bug detection, we analyze the debug information to reconstruct network traffic. We also provide relevant statistics for debugging, such as packet interactions and packet latencies, per router. In our experiments, this approach allows us to reconstruct over 80% of the packets' routes. Moreover, the obtained statistics facilitate debugging erroneous network behavior and identifying performance bottlenecks

A probabilistic approach to early communication performance estimation for electronic system-level design

Today\u27s embedded system designers face the challenges of ever increasing complexity and shorter time-to-market deadlines. System-level methodologies emerge to meet these challenges. Refinement-based methodologies, such as the SpecC methodology and Transaction Level Modeling, continue to gain popularity in the embedded system designers\u27 community. However, as more communication-dominated applications and architectures appear in the market, designers find that the lack of models allowing system-level communication analysis is a major limiting factor in current system-level design methodologies. Thus, modeling for system-level communication analysis is key for a design methodology to thrive with today\u27s embedded system designers. This work presents a new approach to system-level modeling that allows better communication analysis earlier in the design process. This approach defines a new model that utilizes random variables to include the communication details at higher abstraction levels. This work proposes a probabilistic model to include and evaluate the system communication features in the higher abstraction level. Guidelines to include the proposed model into a refinement-based methodology are presented, and methods for performance estimation are shown