Architectural Improvements Towards an Efficient 16-18 Bit 100-200 MSPS ADC

As Data conversion systems continue to improve in speed and resolution, increasing demands are placed on the performance of high-speed Analog to Digital Conversion systems. This work makes a survey about all these and proposes a suitable architecture in order to achieve the desired specifications of 100-200MS/s with 16-18 bit of resolution. The main architecture is based on paralleled structures in order to achieve high sampling rate and at the same time high resolution. In order to solve problems related to Time-interleaved architectures, an advanced randomization method was introduced. It combines randomization and spectral shaping of mismatches. With a simple low-pass filter the method can, compared to conventional randomization algorithms, improve the SFDR as well as the SINAD. The main advantage of this technique over previous ones is that, because the algorithm only need that ADCs are ordered basing on their time mismatches, the absolute accuracy of the mismatch identification method does not matter and, therefore, the requirements on the timing mismatch identification are very low. In addition to that, this correction system uses very simple algorithms able to correct not only for time but also for gain and offset mismatches

Time-Interleaved Analog-to-Digital Converter (TIADC) Compensation Using Multichannel Filters

Published methods that employ a filter bank for compensating the timing and bandwidth mismatches of an M-channel time-interleaved analog-to-digital converter (TIADC) were developed based on the fact that each sub-ADC channel is a downsampled version of the analog input. The output of each sub-ADC is filtered in such a way that, when all the filter outputs are summed, the aliasing components are minimized. If each channel of the filter bank has N coefficients, the optimization of the coefficients requires computing the inverse of an MN times MN matrix if the weighted least squares (WLS) technique is used as the optimization tool. In this paper, we present a multichannel filtering approach for TIADC mismatch compensation. We apply the generalized sampling theorem to directly estimate the ideal output of each sub-ADC using the outputs of all the sub-ADCs. If the WLS technique is used as the optimization tool, the dimension of the matrix to be inversed is N times N. For the same number of coefficients (and also the same spurious component performance given sufficient arithmetic precision), our technique is computationally less complex and more robust than the filter-bank approach. If mixed integer linear programming is used as the optimization tool to produce filters with coefficient values that are integer powers of two, our technique produces a saving in computing resources by a factor of approximately (100.2N(M- 1)/(M-1) in the TIADC filter design.published_or_final_versio

Iterative correction of frequency response mismatches in time-interleaved ADCs: A novel framework and case study in OFDM systems

In this paper, we study a versatile iterative framework for the correction of frequency response mismatch in time-interleaved ADCs. Based on a general time varying linear system model, we establish a flexible iterative framework, which enables the development of various efficient iterative correction algorithms. In particular, we study the Gauss-Seidel iteration in detail to illustrate how the correction problem can be solved iteratively, and show that the iterative structure can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. Simulation results show that the proposed iterative structure performs better than conventional compensation structures. Moreover, a preliminary study on the BER performance of OFDM systems due to TI ADC mismatch is conducted. © 2010 IEEE.published_or_final_versionThe 1st International Conference on Green Circuits and Systems (ICGCS 2010), Shanghai, China, 21-23 June 2010. In Proceedings of the 1st ICGCS, 2010, p. 253-25

New iterative framework for frequency response mismatch correction in time-interleaved ADCs: Design and performance analysis

This paper proposes a new iterative framework for the correction of frequency response mismatch in time-interleaved analog-to-digital converters. Based on a general time-varying linear system model for the mismatch, we treat the reconstruction problem as a linear inverse problem and establish a flexible iterative framework for practical implementation. It encumbrances a number of efficient iterative correction algorithms and simplifies their design, implementation, and performance analysis. In particular, an efficient Gauss-Seidel iteration is studied in detail to illustrate how the correction problem can be solved iteratively and how the proposed structure can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. We also study important issues, such as the sufficient convergence condition and reconstructed signal spectrum, derive new lower bound of signal-to-distortion-and-noise ratio in order to ensure stable operation, and predict the performance of the proposed structure. Furthermore, we propose an extended iterative structure, which is able to cope with systems involving more than one type of mismatches. Finally, the theoretical results and the effectiveness of the proposed approach are validated by means of computer simulations. © 2011 IEEE.published_or_final_versio

Methodology for Mismatch Reduction in Time-Interleaved ADCs

This paper presents a methodology to minimize mismatch errors in time-interleaved analog-to-digital converters (ADC) by means of averaging multiple channels. A simple algorithm improving both spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SINAD) is demonstrated. The presented technique provides robustness against inaccurately identified mismatch errors and does not require computationally expensive post-processing of the signal

Post Conversion Correction of Non-Linear Mismatches for Time Interleaved Analog-to-Digital Converters

Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the approaches discussed here are independent of architecture; some solutions take advantage of specific architectures. Chapter 1 provides the problem formulation and reviews the errors found in ADCs as well as a brief literature review of available TI-ADC error correction solutions. Chapter 2 presents the methods and materials used in implementation as well as extend the state of the art for post conversion correction. Chapter 3 presents the simulation results of this work and Chapter 4 concludes the work. The contribution of this research is three fold: A new behavioral model was developed in SimulinkTM and MATLABTM to model and test linear and nonlinear mismatch errors emulating the performance data of actual converters. The details of this model are presented as well as the results of cumulant statistical calculations of the mismatch errors which is followed by the detailed explanation and performance evaluation of the extension developed in this research effort. Leading post conversion correction methods are presented and an extension with derivations is presented. It is shown that the data converter subsystem architecture developed is capable of realizing better performance of those currently reported in the literature while having a more efficient implementation

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method