16,883 research outputs found
Open-ended evolution to discover analogue circuits for beyond conventional applications
This is the author's accepted manuscript. The final publication is available at Springer via http://dx.doi.org/10.1007/s10710-012-9163-8. Copyright @ Springer 2012.Analogue circuits synthesised by means of open-ended evolutionary algorithms often have unconventional designs. However, these circuits are typically highly compact, and the general nature of the evolutionary search methodology allows such designs to be used in many applications. Previous work on the evolutionary design of analogue circuits has focused on circuits that lie well within analogue application domain. In contrast, our paper considers the evolution of analogue circuits that are usually synthesised in digital logic. We have developed four computational circuits, two voltage distributor circuits and a time interval metre circuit. The approach, despite its simplicity, succeeds over the design tasks owing to the employment of substructure reuse and incremental evolution. Our findings expand the range of applications that are considered suitable for evolutionary electronics
Evolutionary Synthesis of Analog Electronic Circuits Using EDA Algorithms
DisertaÄnĂ prĂĄce je zamÄĹena na nĂĄvrh analogovĂ˝ch elektronickĂ˝ch obvodĹŻ pomocĂ algoritmĹŻ s pravÄpodobnostnĂmi modely (algoritmy EDA). PrezentovanĂŠ metody jsou na zĂĄkladÄ poĹžadovanĂ˝ch charakteristik cĂlovĂ˝ch obvodĹŻ schopny navrhnout jak parametry pouĹžitĂ˝ch komponent tak takĂŠ jejich topologii zapojenĂ. TĹi rĹŻznĂŠ metody vyuĹžitĂ EDA algoritmĹŻ jsou navrĹženy a otestovĂĄny na pĹĂkladech skuteÄnĂ˝ch problĂŠmĹŻ z oblasti analogovĂ˝ch elektronickĂ˝ch obvodĹŻ. PrvnĂ metoda je urÄena pro nĂĄvrh pasivnĂch analogovĂ˝ch obvodĹŻ a vyuĹžĂvĂĄ algoritmus UMDA pro nĂĄvrh jak topologie zapojenĂ tak takĂŠ hodnot parametrĹŻ pouĹžitĂ˝ch komponent. Metoda je pouĹžita pro nĂĄvrh admitanÄnĂ sĂtÄ s poĹžadovanou vstupnĂ impedancĂ pro ĂşÄely chaotickĂŠho oscilĂĄtoru. DruhĂĄ metoda je takĂŠ urÄena pro nĂĄvrh pasivnĂch analogovĂ˝ch obvodĹŻ a vyuĹžĂvĂĄ hybridnĂ pĹĂstup - UMDA pro nĂĄvrh topologie a metodu lokĂĄlnĂ optimalizace pro nĂĄvrh parametrĹŻ komponent. TĹetĂ metoda umoĹžĹuje nĂĄvrh analogovĂ˝ch obvodĹŻ obsahujĂcĂch takĂŠ tranzistory. Metoda vyuĹžĂvĂĄ hybridnĂ pĹĂstup - EDA algoritmus pro syntĂŠzu topologie a metoda lokĂĄlnĂ optimalizace pro urÄenĂ parametrĹŻ pouĹžitĂ˝ch komponent. Informace o topologii je v jednotlivĂ˝ch jedincĂch populace vyjĂĄdĹena pomocĂ grafĹŻ a hypergrafĹŻ.Dissertation thesis is focused on design of analog electronic circuits using Estimation of Distribution Algorithms (EDA). Based on the desired characteristics of the target circuits the proposed methods are able to design the parameters of the used components and theirs topology of connection as well. Three different methods employing EDA algorithms are proposed and verified on examples of real problems from the area of analog circuits design. The first method is capable to design passive analog circuits. The method employs UMDA algorithm which is used for determination of the parameters of the used components and synthesis of the topology of their connection as well. The method is verified on the problem of design of admittance network with desired input impedance function which is used as a part of chaotic oscillator circuit. The second method is also capable to design passive analog circuits. The method employs hybrid approach - UMDA for synthesis of the topology and local optimization method for determination of the parameters of the components. The third method is capable to design analog circuits which include also ac- tive components such as transistors. Hybrid approach is used. The topology is synthesized using EDA algorithm and the parameters are determined using a local optimization method. In the individuals of the population information about the topology is represented using graphs and hypergraphs.
Generalized disjunction decomposition for evolvable hardware
Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the âgeneralized disjunction decompositionâ (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using theevolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided
Evolutionary Synthesis of Fractional Capacitor Using Simulated Annealing Method
Synthesis of fractional capacitor using classical analog circuit synthesis method was described in [6]. The work presented in this paper is focused on synthesis of the same problem by means of evolutionary method simulated annealing. Based on given desired characteristic function as input impedance or transfer function, the proposed method is able to synthesize topology and values of the components of the desired analog circuit. Comparison of the results given in [6] and results obtained by the proposed method will be given and discussed
A novel genetic algorithm for evolvable hardware
Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures
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On evolution of relatively large combinational logic circuits
Evolvable hardware (EHW) (Yao and Higuchi, 1999) is a technique introduced to automatically design circuits where the circuit configuration is carried out by evolutionary algorithms. One of the main difficulties in using EHW to solve real-world problems is the scalability. Until now, several strategies have been proposed to avoid this problem, but none of them completely tackle the issue. In this paper three different methods for evolving the most complex circuits have been tested for their scalability. These methods are bi-directional incremental evolution (SO-BIE); generalised disjunction decomposition (GD-BIE) and evolutionary strategies (ES) with dynamic mutation rate. In order to achieve the generalised conclusions the chosen approaches were tested using multipliers, traditionally used in EHW, but also logic circuits taken from MCNC (Yang, 1991) benchmark library and randomly generated circuits. The analysis of the approaches demonstrated that PLA-based ES is capable of evolving logic circuits of up to 12 inputs. The use of SO-BIE allows the generation of fully functional circuits of 14 inputs and GD-BIE is estimated to be able to evolve circuits of 21 inputs
Improving EHW performance introducing a new decomposition strategy
This paper describes a new type of decomposition strategy for Evolvable Hardware, which tackles the problem of scalability. Several logic circuits from the MCNC benchmark have been evolved and compared with other Evolvable Hardware techniques. The results demonstrate that the proposed method improves the evolution of logic circuits in terms of time and fitness function in comparison with BIE and standard EHW
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