Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Fully-integrated mm-Wave Full-duplexing and MIMO Multi-beamforming Receiver Techniques for 5G and Beyond

In recent years, the research community's interest in fully integrated mm-Wave wireless communication systems has increased significantly. With the standards for 5G NR now in place, the focus has shifted to actual deployment. Mm-Wave systems provide wider bandwidths, higher capacity, and lower latency than existing systems such as 4G. Higher path loss and shadowing, however, limit the network coverage at mm-Wave frequencies. The possibility of beamforming due to compact antenna size at mm-Wave and range-extending repeaters help mitigate challenges arising from path loss and relax link budget requirements. In the first part of the thesis, fully integrated scalable MIMO multi-beamforming phased-array to enable unit-tile based densely packed (lambda=2) large scale phased-arrays is demonstrated. Large scale arrays enhance Signal to Noise Ratio (SNR) and/or Effective Isotropically Radiated Power (EIRP) and help meet link budget. In the second part, mm-Wave Full-duplex (FD) receiver (RX) to implement Integrated Access and Backhaul (IAB) and repeaters in a spectrum efficient way is demonstrated. Dense deployment of IAB and repeaters enhances link robustness and range of connectivity. Two Integrated Chips (ICs) are fabricated and measured for demonstration. In the first IC, a 4-element MIMO RX array with multi-beamforming and simplified single wire intermediate frequency (IF) IO is presented. The evolution of mm-wave phased array receivers to MIMO RX promises multi-beamforming and improved capacity. Digital Beamforming (DBF) provides the highest flexibility for multibeamforming. However, it suffers from # of ADCs scaling with the # of elements and absence of spatial filtering prior to the ADCs. Mm-Wave MIMO arrays must also address the challenge of increased IO routing while supporting dense ll-factors with =2 antenna spacing. In this work, a MIMO multi-beamforming RX array architecture with simultaneous spatial filtering and single wire Frequency-domain Multiplexing (FDM) for 5G and beyond is presented. The proposed system preserves full MIMO field-of-view while ensuring a single IF interface. A 28 GHz 4-element RX prototype demonstrates the proposed functionality in 65-nm CMOS. The IC occupies only 3.4mm x 3.1mm for a four-element MIMO 28 GHz array and can form four independent beams with > 400MHz 3 dB BW and FDM on to a single IF interface. Mm-wave MIMO operation is demonstrated by concurrent reception of two wireless 28 GHz beams at 400 Mb/s (100 Msps, 16QAM) data rate. In the second IC, a 26-GHz fully integrated In-band Full-duplex (IBFD) Circulator receiver, which employs passive and active Self-interference Cancellation (SIC) techniques in the mm-Wave domain is presented. Coverage of wireless networks at mm-Wave frequencies can be enhanced by deploying a large number of base stations economically using wireless backhauling. Integrated access and backhaul nodes with spectrum reuse is an efficient way of wireless backhauling. To retain the channel capacity, IAB needs to be implemented using FD schemes that suffers from a strong Transmitter (TX) to RX leakage. This SI leakage can significantly impact the receiver sensitivity and increase the baseband/ADC dynamic range requirements. Canceling SI at mm-Wave applications is challenging given the high frequency of operation, wide bandwidths, and antenna (ANT) impedance sensitivity to the surroundings. Proposed mm-Wave RX with a shared ANT interface based on a Circulator with active SI cancelers provide ~53 dB SIC over 400MHz and ~40 dB SIC over 400MHz to meet the link budget requirements. Proposed architecture achieves SIC by (i) introducing a shared ANT interface based on a hybrid-coupler and a Non-reciprocal Transmission Line (NTL) that provides wideband SIC and additionally creating a SI replica (ii) subsequent active cancellation using SI replica along with variable gain and phase shifters to accommodate SI channel variations. Proposed 26-GHz RX consumes only ~111mW power. The system is implemented in 45nm SOI CMOS and has an active area of 4.54mm². Stand-alone RX NF is ~5.8 dB, and TX to ANT Insertion Loss (IL) is ~3.1 dB. Over-the-Air (OTA) measurements with modulated TX (128 QAM 2.1 Gb/s) and RX (128 QAM 4.2 Gb/s) signals show an EVM of 3.3% when PTX = PRX

Design methods for 60GHz beamformers in CMOS

The 60GHz band is promising for applications such as high-speed short-range wireless personal-area network (WPAN), real-time video streaming at rates of several-Gbps, automotive radar, and mm-Wave imaging, since it provides a large amount of bandwidth that can freely (i.e. without a license) be used worldwide. However, transceivers at 60GHz pose several additional challenges over microwave transceivers. In addition to the circuit design challenges of implementing high performance 60GHz RF circuits in mainstream CMOS technology, the path loss at 60GHz is significantly higher than at microwave frequencies because of the smaller size of isotropic antennas. This can be overcome by using phased array technology. This thesis studies the new concepts and design techniques that can be used for 60GHz phased array systems. It starts with an overview of various applications at mm-wave frequencies, such as multi-Gbps radio at 60GHz, automotive radar and millimeter-wave imaging. System considerations of mm-wave receivers and transmitters are discussed, followed by the selection of a CMOS technology to implement millimeter-wave (60GHz) systems. The link budget of a 60GHz WPAN is analyzed, which leads to the introduction of phased array techniques to improve system performance. Different phased array architectures are studied and compared. The system requirements of phase shifters are discussed. Several types of conventional RF phase shifters are reviewed. A 60GHz 4-bit passive phase shifter is designed and implemented in a 65nm CMOS technology. Measurement results are presented and compared to published prior art. A 60GHz 4-bit active phase shifter is designed and integrated with low noise amplifier and combiner for a phased array receiver. This is implemented in a 65nm CMOS technology, and the measurement results are presented. The design of a 60GHz 4-bit active phase shifter and its integration with power amplifier is also presented for a phased array transmitter. This is implemented in a 65nm CMOS technology. The measurement results are also presented and compared to reported prior art. The integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package is investigated. Experimental results are presented and discussed

Integrated Circuit and Antenna Technology for Millimeter-wave Phased Array Radio Front-end

Ever growing demands for higher data rate and bandwidth are pushing extremely high data rate wireless applications to millimeter-wave band (30-300GHz), where sufficient bandwidth is available and high data rate wireless can be achieved without using complex modulation schemes. In addition to the communication applications, millimeter-wave band has enabled novel short range and long range radar sensors for automotive as well as high resolution imaging systems for medical and security. Small size, high gain antennas, unlicensed and worldwide availability of released bands for communication and a number of other applications are other advantages of the millimeter-wave band. The major obstacle for the wide deployment of commercial wireless and radar systems in this frequency range is the high cost and bulky nature of existing GaAs- and InP-based solutions. In recent years, with the rapid scaling and development of the silicon-based integrated circuit technologies such as CMOS and SiGe, low cost technologies have shown acceptable millimeter-wave performance, which can enable highly integrated millimeter-wave radio devices and reduce the cost significantly. Furthermore, at this range of frequencies, on-chip antenna becomes feasible and can be considered as an attractive solution that can further reduce the cost and complexity of the radio package. The propagation channel challenges for the realization of low cost and reliable silicon-based communication devices at millimeter-wave band are severe path loss as well as shadowing loss of human body. Silicon technology challenges are low-Q passive components, low breakdown voltage of active devices, and low efficiency of on-chip antennas. The main objective of this thesis is to investigate and to develop antenna and front-end for cost-effective silicon based millimeter-wave phased array radio architectures that can address above challenges for short range, high data rate wireless communication as well as radar applications. Although the proposed concepts and the results obtained in this research are general, as an important example, the application focus in this research is placed on the radio aspects of emerging 60 GHz communication system. For this particular but extremely important case, various aspects of the technology including standard, architecture, antenna options and indoor propagation channel at presence of a human body are studied. On-chip dielectric resonator antenna as a radiation efficiency improvement technique for an on-chip antenna on low resistivity silicon is presented, developed and proved by measurement. Radiation efficiency of about 50% was measured which is a significant improvement in the radiation efficiency of on-chip antennas. Also as a further step, integration of the proposed high efficiency antenna with an amplifier in transmit and receive configurations at 30 GHz is successfully demonstrated. For the implementation of a low cost millimeter-wave array antenna, miniaturized, and efficient antenna structures in a new integrated passive device technology using high resistivity silicon are designed and developed. Front-end circuit blocks such as variable gain LNA, continuous passive and active phase shifters are investigated, designed and developed for a 60GHz phased array radio in CMOS technology. Finally, two-element CMOS phased array front-ends based on passive and active phase shifting architectures are proposed, developed and compared

Circuit Design Techniques For Wideband Phased Arrays

University of Minnesota Ph.D. dissertation.June 2015. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xii, 143 pages.This dissertation focuses on beam steering in wideband phased arrays and phase noise modeling in injection locked oscillators. Two different solutions, one in frequency and one in time, have been proposed to minimize beam squinting in phased arrays. Additionally, a differential current reuse frequency doubler for area and power savings has been proposed. Silicon measurement results are provided for the frequency domain solution (IBM 65nm RF CMOS), injection locked oscillator model verification (IBM 130nm RF-CMOS) and frequency doubler (IBM 65nm RF CMOS), while post extraction simulation results are provided for the time domain phased array solution (the chip is currently under fabrication, TSMC 65nm RF CMOS). In the frequency domain solution, a 4-point passive analog FFT based frequency tunable filter is used to channelize an incoming wideband signal into multiple narrowband signals, which are then processed through independent phase shifters. A two channel prototype has been developed at 8GHz RF frequency. Three discrete phase shifts (0 & +/- 90 degrees) are implemented through differential I-Q swapping with appropriate polarity. A minimum null-depth of 19dB while a maximum null-depth of 27dB is measured. In the time domain solution, a discrete time approach is undertaken with signals getting sampled in order of their arrival times. A two-channel prototype for a 2GHz instantaneous RF bandwidth (7GHz-9GHz) has been designed. A QVCO generates quadrature LO signals at 8GHz which are phase shifted through a 5-bit (2 extra bits from differential I-Q swapping with appropriate polarity) cartesian combiner. Baseband sampling clocks are generated from phase shifted LOs through a CMOS divide by 4 with independent resets. The design achieves an average time delay of 4.53ps with 31.5mW of power consumption (per channel, buffers excluded). An injection locked oscillator has been analyzed in s-domain using Paciorek's time domain transient equations. The simplified analysis leads to a phase noise model identical to that of a type-I PLL. The model is equally applicable to injection locked dividers and multipliers and has been extended to cover all injection locking scenarios. The model has been verified against a discrete 57MHz Colpitt's ILO, a 6.5GHz ILFD and a 24GHz ILFM with excellent matching between the model and measurements. Additionally, a differential current reuse frequency doubler, for frequency outputs between 7GHz to 14GHz, design has been developed to reduce passive area and dc power dissipation. A 3-bit capacitive tuning along with a tail current source is used to better conversion efficiency. The doubler shows FOM$_{T}$ values between 191dBc/Hz to 209dBc/Hz when driven by a 0.7GHz to 5.8GHz wide tuning VCO with a phase noise that ranges from -114dBc/Hz to -112dBc/Hz over the same bandwidth

High-Performance Multi-Antenna Wireless for 5G and Beyond

Over the next decade, multi-antenna radios, including phased array and multiple-input-multiple-output (MIMO) radios, are expected to play an essential role in the next-generation of wireless networks. Phased arrays can reject spatial interferences and provide coherent beamforming gain, and MIMO technology promises to significantly enhance the system performance in the coverage, capacity, and user data rate through the beamforming or diversity/capacity gain which can substantially increase the range in wireless links, that are challenged from the transmitter (TX) power handling, receiver (RX) noise perspectives and a multi-path environment. Furthermore, the multi-user MIMO (MU-MIMO) can simultaneously serve multiple users which is vital for femtocell base stations and access points (AP). Full-duplex (FD) wireless, namely simultaneous transmission and reception at the same frequency, is an emerging technology that has gained attention due to its potential to double the data throughput, as well as provide other benefits in the higher layers such as better spectral efficiency, reducing network and feedback signaling delays, and resolving hidden-node problems to avoid collisions. However, several challenges remain in the quest for the high-performance integrated FD radios. Transmitter power handling remains an open problem, particularly in FD radios that integrate a shared antenna interface. Secondly, FD operation must be achieved across antenna VSWR variations and a changing EM environment. Finally, FD must be extended to multi-antenna radios, including phased array and multi-input multi-output (MIMO) radios, as over the next decade, they are expected to play an essential role in the next generation of wireless networks. Multi-antenna FD operation, however, is challenged not only by the self-interference (SI) from each TX to its own RX but also cross-talk SI (CT-SI) between antennas. In this dissertation, first, a full-duplex phased array circulator-RX (circ.-RX) is proposed that achieves self-interference cancellation (SIC) through repurposing beamforming degrees of freedom (DoF) on TX and RX. Then, an FD MIMO circ.-RX is proposed that achieves SI and CT-SI cancellation (CT-SIC) through passive RF and shared-delay baseband (BB) canceller that addresses challenges associated with FD MIMO operation. Wireless radios at millimeter-wave (mm-wave) frequencies enable the high-speed link for portable devices due to the wide-band spectrum available. Large-scale arrays are required to compensate for high path loss to form an mm-wave link. Mm-wave MIMO systems with digitization enable virtual arrays for radar, digital beamforming (DBF) for high mobility scenarios and spatial multiplexing. To preserve MIMO information, the received signal from each element in MIMO RX should be transported to ADC/DSP IC for DBF, and vice versa on the TX side. A large-scale array can be formed by tiling multiple mm-wave IC front-ends, and thus, a single-wire interface is desired between DSP IC and mm-wave ICs to reduce board routing complexity. Per-element digitization poses the challenge of handling high data-rate I/O in large-scale tiled MIMO mm-wave arrays. SERializer – DESerializer (SERDES) is traditionally being used as a high-speed link in computing systems and networks. However, SERDES results in a large area and power consumption. In this dissertation, a 60~GHz 4-element MIMO TX with a single-wire interface is presented that de-multiplexes the baseband signal of all elements and LO reference that are frequency-domain multiplexed on a single-wire coax cable

RF and Millimeter-wave Techniques to Improve Scalability and Efficiency of Digital Beamforming Arrays

Spectrum overcrowding, ever increasing demand for high data rate and increased mobility requirements are three major challenges 5G-technology is trying to address. In this thesis I start with a RF front-end technique that deals with blocker interference arising from spectrum overcrowding both across frequency bands and within the same frequency bands. Chapter 3 presents a single wire IF interface design for phased array receivers which enables simple IF backhaul for high data volume MIMO systems. Finally a outphasing power amplifier(PA) design is presented in chapter 4 along with a driver amplifier with digital amplitude modulation to achieve state of the art power back off efficiency, which reduces battery usage and thus increases mobility. The first part of this thesis demonstrates the use of orthogonal sequences along to N-path filters to achieve reconfigurable select/reject filtering of signals based on their spatial, spectral and code-domain properties. A frequency/code-domain reject and select filtering is proposed and implemented using N-path switching with passive inductors as correlators. Using inductors instead of capacitors in N-path filters is challenging because of large inductance value required for our application demands use of off-chip inductors, which comes with associated parasitics and lower self-resonance frequency. In this design a cascaded inductor approach and differential N-path filtering is used to overcome inductor parasitics and enable operation at 1 GHz. A code-domain notch filter followed by a code-domain select receiver is designed and implemented in 65-nm CMOS technology. Measurements demonstrate 0.5 GHz to 1.0 GHz filter tuning range, with a maximum 26dB rejection for a blocker signal with 8dBm power, while consuming 60mW (at 1GHz operation frequency) and occupying 1.2mm2 of die area. Second part of this thesis demonstrates a single wire IF interface to simplify scaling of millimeter-wave(mm-Wave) phased array systems while preserving the data from each element, this enables spatial multiplexing, virtual arrays for radar, digital beamforming(DBF), etc. However, per-element digitization results in a formidable I/O challenge in large-scale tiled MIMO mm-Wave arrays. This dissertation demonstrates a 28 GHz 4-element MIMO RX with a single-wire interface that multiplexes the baseband signals of all elements and the LO reference through code-domain multiplexing. System considerations are presented and the approach is validated through DBF after de-multiplexing of the baseband signals from the single wire. Each element in the array achieves 16 dB conversion gain and ∼ 7 dB noise figure(NF) while consuming 60 mA from 1.2 V. The IC occupies 5.75 mm² in 65-nm CMOS. Final part of this thesis describes the design and implementation of a digital outphasing PA at 28 GHz to achieve state of the art back of efficiency. Outphasing PA require branch PA units to act as voltage sources(very low output impedance), which is challenging at mm-Wave frequencies. In this PA design an approximate class-F operation is achieved by tuning PA load network for up to 3rd harmonic. A stacked PA architecture is used for individual PA units to achieve high maximum power output. Output-power further improved by utilizing a novel diode connected stack bias circuit to improve out-put swing. PA delivers a maximum output-power of 20 dBm with a peak power added efficiency(PAE) of 27% (PA along with driver stages) and 6 dB back-off PAE of 16.5%

Architectures and Integrated Circuits for Efficient, High-power "Digital'' Transmitters for Millimeter-wave Applications

This thesis presents architectures and integrated circuits for the implementation of energy-efficient, high-power "digital'' transmitters to realize high-speed long-haul links at millimeter-wave frequencies in nano-scale silicon-based processes