15 research outputs found
A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning
Nanoscale resistive memories are expected to fuel dense integration of
electronic synapses for large-scale neuromorphic system. To realize such a
brain-inspired computing chip, a compact CMOS spiking neuron that performs
in-situ learning and computing while driving a large number of resistive
synapses is desired. This work presents a novel leaky integrate-and-fire neuron
design which implements the dual-mode operation of current integration and
synaptic drive, with a single opamp and enables in-situ learning with crossbar
resistive synapses. The proposed design was implemented in a 0.18 m CMOS
technology. Measurements show neuron's ability to drive a thousand resistive
synapses, and demonstrate an in-situ associative learning. The neuron circuit
occupies a small area of 0.01 mm and has an energy-efficiency of 9.3
pJspikesynapse
A Compact CMOS Memristor Emulator Circuit and its Applications
Conceptual memristors have recently gathered wider interest due to their
diverse application in non-von Neumann computing, machine learning,
neuromorphic computing, and chaotic circuits. We introduce a compact CMOS
circuit that emulates idealized memristor characteristics and can bridge the
gap between concepts to chip-scale realization by transcending device
challenges. The CMOS memristor circuit embodies a two-terminal variable
resistor whose resistance is controlled by the voltage applied across its
terminals. The memristor 'state' is held in a capacitor that controls the
resistor value. This work presents the design and simulation of the memristor
emulation circuit, and applies it to a memcomputing application of maze solving
using analog parallelism. Furthermore, the memristor emulator circuit can be
designed and fabricated using standard commercial CMOS technologies and opens
doors to interesting applications in neuromorphic and machine learning
circuits.Comment: Submitted to International Symposium of Circuits and Systems (ISCAS)
201
Spiking neural network Based on cusp catastrophe Theory
This paper addresses the problem of effective processing using third generation neural networks. The article features two new models of spiking neurons based on the cusp catastrophe theory. The effectiveness of the models is demonstrated with an example of a network composed of three neurons solving the problem of linear inseparability of the XOR function. The proposed solutions are dedicated to hardware implementation using the Edge computing strategy. The paper presents simulation results and outlines further research direction in the field of practical applications and implementations using nanometer cMOS technologies and the current processing mode.publishersversionpublishe
Hardware design of LIF with Latency neuron model with memristive STDP synapses
In this paper, the hardware implementation of a neuromorphic system is
presented. This system is composed of a Leaky Integrate-and-Fire with Latency
(LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL
neuron model allows to encode more information than the common
Integrate-and-Fire models, typically considered for neuromorphic
implementations. In our system LIFL neuron is implemented using CMOS circuits
while memristor is used for the implementation of the STDP synapse. A
description of the entire circuit is provided. Finally, the capabilities of the
proposed architecture have been evaluated by simulating a motif composed of
three neurons and two synapses. The simulation results confirm the validity of
the proposed system and its suitability for the design of more complex spiking
neural network
Temporal-Coded Deep Spiking Neural Network with Easy Training and Robust Performance
Spiking neural network (SNN) is interesting both theoretically and
practically because of its strong bio-inspiration nature and potentially
outstanding energy efficiency. Unfortunately, its development has fallen far
behind the conventional deep neural network (DNN), mainly because of difficult
training and lack of widely accepted hardware experiment platforms. In this
paper, we show that a deep temporal-coded SNN can be trained easily and
directly over the benchmark datasets CIFAR10 and ImageNet, with testing
accuracy within 1% of the DNN of equivalent size and architecture. Training
becomes similar to DNN thanks to the closed-form solution to the spiking
waveform dynamics. Considering that SNNs should be implemented in practical
neuromorphic hardwares, we train the deep SNN with weights quantized to 8, 4, 2
bits and with weights perturbed by random noise to demonstrate its robustness
in practical applications. In addition, we develop a phase-domain signal
processing circuit schematic to implement our spiking neuron with 90% gain of
energy efficiency over existing work. This paper demonstrates that the
temporal-coded deep SNN is feasible for applications with high performance and
high energy efficient
Analog Spiking Neural Network Implementing Spike Timing-Dependent Plasticity on 65 nm CMOS
Machine learning is a rapidly accelerating tool and technology used for countless applications in the modern world. There are many digital algorithms to deploy a machine learning program, but the most advanced and well-known algorithm is the artificial neural network (ANN). While ANNs demonstrate impressive reinforcement learning behaviors, they require large power consumption to operate. Therefore, an analog spiking neural network (SNN) implementing spike timing-dependent plasticity is proposed, developed, and tested to demonstrate equivalent learning abilities with fractional power consumption compared to its digital adversary