A Foundation for Development of Programming Languages for Real-Time Systems

Applications of real-time systems have grown considerably in both diversity and popularity, and the demand for real-time software has never been higher. In contrast, the choice of programming languages used to develop these systems has mostly remained limited to decades-old languages, namely Ada and C/C++, and more recently real-time Java. We postulate that the main reason for this mono-culture is the difficulty of developing new programming languages for real-time systems, due to their strict correctness requirements. Wang et al. argue that implementing even general-purpose languages is not easy, and is the source of many problems in today's languages. They propose the Micro Virtual Machine as a minimal abstraction layer to relieve the challenges of implementing a managed language, and design a micro VM specification named Mu. Compared to conventional language VMs, a micro VM is minimal and low-level. This makes micro VM an appealing idea towards creating a platform for development of programming languages for real-time systems, as it allows supporting a wide range of languages, aligned with the huge diversity of real-time systems. It also makes correct implementation and formal verification of the platform easier, which is vital for many real-time systems. Prior to this thesis, the only concrete micro VM specification was [Mu, 2018]. However,Mu is not designed for real-time systems and lacks some of the essential features. My thesis is that a real-time-enabled micro virtual machine is capable of providing an efficient and usable foundation for development of program-ming languages, suitable for building real-time software. The first high-level contribution of this thesis is the design of RTMu, a micro VM instance aiming at programming languages for real-time systems. We build on the Mu specification and propose a set of modifications to its abstractions over concurrency and memory management to make it suitable for real-time systems. The second contribution is the affirmation of the implementability of the RTMu's abstractions. For this purpose, we build a high-performance implementation of the RTMu specification, based-on a high-performance implementation of Mu. The third contribution is the design of a real-time extension to RPython, to make it a fully-featured language for real-time systems, named RT-RPython. We implement RT-RPython on top of RTMu and evaluate its performance through the CollisionDetection benchmark suite. This thesis is a proof of concept for establishing the use of micro VMs to build new high-quality programming languages for real-time systems. It also provides empirical demonstration of performance and predictability for micro VMs in the real-time domain. We believe that RTMu can help in tackling the current lack of diversity in programming languages for real-time systems

High Level Synthesis of Neural Network Chips

This thesis investigates the development of a silicon compiler dedicated to generate Application-Specific Neural Network Chips (ASNNCs) from a high level C-based behavioural specification language. The aim is to fully integrate the silicon compiler with the ESPRIT II Pygmalion neural programming environment. The integration of these two tools permits the translation of a neural network application specified in nC, the Pygmalion's C-based neural programming language, into either binary (for simulation) or silicon (for execution in hardware). Several applications benefit from this approach, in particular the ones that require real-time execution, for which a true neural computer is required. This research comprises two major parts: extension of the Pygmalion neural programming environment, to support automatic generation of neural network chips from the nC specification language; and implementation of the high level synthesis part of the neural silicon compiler. The extension of the neural programming environment has been developed to adapt the nC language to hardware constraints, and to provide the environment with a simulation tool to test in advance the performance of the neural chips. Firstly, new hardware-specific requisites have been incorporated to nC. However, special attention has been taken to avoid transforming nC into a hardware-oriented language, since the system assumes minimum (or even no) knowledge of VLSI design from the application developer. Secondly, a simulator for neural network hardware has been developed, which assesses how well the generated circuit will perform the neural computation. Lastly, a hardware library of neural network models associated with a target VLSI architecture has been built. The development of the neural silicon compiler focuses on the high level synthesis part of the process. The goal of the silicon compiler is to take nC as the input language and automatically translate it into one or more identical integrated circuits, which are specified in VHDL (the IEEE standard hardware description language) at the register transfer level. The development of the high level synthesis comprises four major parts: firstly, compilation and software-like optimisations of nC; secondly, transformation of the compiled code into a graph-based internal representation, which has been designed to be the basis for the hardware synthesis; thirdly, further transformations and hardware-like optimisations on the internal representation; and finally, creation of the neural chip's data path and control unit that implement the behaviour specified in nC. Special attention has been devoted to the creation of optimised hardware structures for the ASNNCs employing both phases of neural computing on-chip: recall and learning. This is achieved through the data path and control synthesis algorithms, which adopt a heuristic approach that targets the generated hardware structure of the neural chip in a specific VLSI architecture, namely the Generic Neuron. The viability, concerning the effective use of silicon area versus speed, has been evaluated through the automatic generation of a VHDL description for the neural chip employing the Back Propagation neural network model. This description is compared with the one created manually by a hardware designer

Database of audio records

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Abstract State Machines 1988-1998: Commented ASM Bibliography

An annotated bibliography of papers which deal with or use Abstract State Machines (ASMs), as of January 1998.Comment: Also maintained as a BibTeX file at http://www.eecs.umich.edu/gasm

Developing Interaction 3D Models for E-Learning Applications

Some issues concerning the development of interactive 3D models for e-learning applications are considered. Given that 3D data sets are normally large and interactive display demands high performance computation, a natural solution would be placing the computational burden on the client machine rather than on the server. Mozilla and Google opted for a combination of client-side languages, JavaScript and OpenGL, to handle 3D graphics in a web browser (Mozilla 3D and O3D respectively). Based on the O3D model, core web technologies are considered and an example of the full process involving the generation of a 3D model and their interactive visualization in a web browser is described. The challenging issue of creating realistic 3D models of objects in the real world is discussed and a method based on line projection for fast 3D reconstruction is presented. The generated model is then visualized in a web browser. The experiments demonstrate that visualization of 3D data in a web browser can provide quality user experience. Moreover, the development of web applications are facilitated by O3D JavaScript extension allowing web designers to focus on 3D contents generation

A compiler extension for parallelizing arrays automatically on the cell heterogeneous processor

This paper describes the approaches taken to extend an array programming language compiler using a Virtual SIMD Machine (VSM) model for parallelizing array operations on Cell Broadband Engine heterogeneous machine. This development is part of ongoing work at the University of Glasgow for developing array compilers that are beneficial for applications in many areas such as graphics, multimedia, image processing and scientific computation. Our extended compiler, which is built upon the VSM interface, eases the parallelization processes by allowing automatic parallelisation without the need for any annotations or process directives. The preliminary results demonstrate significant improvement especially on data-intensive applications