A PCI Express board designed to interface with the electronic phase-2 upgrades of the ATLAS detectors at CERN

Nei prossimi 10 anni è in previsione un aggiornamento radicale dell'acceleratore LHC al CERN finalizzato al raggiungimento di più alti valori di luminosità istantanea (oltre \begin{math}5 \times 10^{34}cm^{-2}s^{-1}\end{math}) ed integrata (oltre un fattore 10 rispetto a quella attuale). Conseguentemente, anche i rilevatori degli esperimenti che lavorano al CERN, così come i loro sistemi di acquisizione dati, dovranno essere aggiornati per poter gestire un flusso notevolmente maggiore rispetto a quello utilizzato finora. Questa tesi tratta in particolare di una nuova scheda elettronica di lettura, progettata e testata nel laboratorio di elettronica del Dipartimento di Fisica ed Astronomia dell'Università di Bologna e nel laboratorio di elettronica della Sezione INFN (Istituto Nazionale di Fisica Nucleare) di Bologna. Le motivazioni che hanno indotto lo sviluppo della scheda prototipale sono molteplici. Un primo obiettivo da perseguire è stato quello di aggiornare la versione attuale delle schede elettroniche di acquisizione dati usate oggi nel Pixel Detector dell'esperimento ATLAS, visto che sono anch'esse sotto la responsabilità della sezione INFN di Bologna. Secondariamente, la scheda (nominata Pixel-ROD) è orientata a gestire le esigenze elettroniche che seguiranno l'upgrade di LHC durante la fase 2. La complessità del progetto e l'inerzia intrinseca di una vasta collaborazione come quella di ATLAS, hanno poi indotto lo sviluppo di questo progetto elettronico in largo anticipo rispetto al vero upgrade di fase 2 di LHC, previsto per il 2024. In questo modo saranno anche più facilmente eseguibili eventuali aggiornamenti tecnologici in corso d'opera, senza dover riprogettare da zero un sistema di acquisizione dati completo

펄스 기반 피드 포워드 이퀄라이저를 갖춘 고용량 DRAM을 위한 컨트롤러 PHY 설계

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 김수환.A controller PHY for managed DRAM solution, which is a new memory structure to maximize capacity while minimizing refresh power, is presented. Inter-symbol interference is critical in such a high-capacity DRAM interface in which many DRAM chips share a command/address (C/A) channel. A pulse-based feed-forward equalizer (PB-FFE) is introduced to reduce ISI on a C/A channel. The controller PHY supports all the training sequences specified in the DDR4 standard. A glitch-free DCDL is also adopted to perform link training efficiently and to reduce training time. The DQ transmitter adopts quarter-rate architecture to reduce output latency. For the quarter-rate transmitters in DQ, we propose a quadrature error corrector (QEC), in which clock signal phase errors are corrected using two replicas of the 4:1 serializer of the output stage. Pulse shrinking is used to compare and equalize the outputs of these two replica serializers. A controller PHY was fabricated in 55nm CMOS. The PB-FFE increases the timing margin from 0.23UI to 0.29UI at 1067Mbps. At 2133Mbps, the read timing and voltage margins are 0.53UI and 211mV after read training, and the write margins are 0.72UI and 230mV after write training. To validate the QEC effectiveness, a prototype quarter-rate transmitter, including the QEC, was fabricated to another chip in 65nm CMOS. Adopting our QEC, the experimental results show that the output phase errors of the transmitter are reduced to a residual error of 0.8ps, and the output eye width and height are improved by 84% and 61%, respectively, at a data-rate of 12.8Gbps.본 연구에서 용량을 최대화하면서도 리프레시 전력을 최소화할 수 있는 새로운 메모리 구조인 관리형 DRAM 솔루션을 위한 컨트롤러 PHY를 제시하였다. 이와 같은 고용량 DRAM 인터페이스에서는 많은 DRAM 칩이 명령 / 주소 (C/A) 채널을 공유하고 있어서 심볼 간 간섭이 발생한다. 본 연구에서는 이러한 C/A 채널에서의 심볼 간 간섭을 줄이기 위해 펄스 기반 피드 포워드 이퀄라이저 (PB-FFE)를 채택하였다. 또한 본 연구의 컨트롤러 PHY는 DDR4 표준에 지정된 모든 트레이닝 시퀀스를 지원한다. 링크 트레이닝을 효율적으로 수행하고 트레이닝 시간을 줄이기 위해 글리치가 발생하지 않는 디지털 제어 지연 라인 (DCDL)을 채택하였다. 컨트롤러 PHY의 DQ 송신기는 출력 대기 시간을 줄이기 위해 쿼터 레이트 구조를 채택하였다. 쿼터 레이트 송신기의 경우에는 직교 클럭 간 위상 오류가 출력 신호의 무결성에 영향을 주게 된다. 이러한 영향을 최소화하기 위해 본 연구에서는 출력 단의 4 : 1 직렬 변환기의 두 복제본을 사용하여 클록 신호 위상 오류를 수정하는 QEC (Quadrature Error Corrector)를 제안하였다. 복제된 2개의 직렬 변환기의 출력을 비교하고 균등화하기 위해 펄스 수축 지연 라인이 사용되었다. 컨트롤러 PHY는 55nm CMOS 공정으로 제조되었다. PB-FFE는 1067Mbps에서 C/A 채널 타이밍 마진을 0.23UI에서 0.29UI로 증가시킨다. 읽기 트레이닝 후 읽기 타이밍 및 전압 마진은 2133Mbps에서 0.53UI 및 211mV이고, 쓰기 트레이닝 후 쓰기 마진은 0.72UI 및 230mV이다. QEC의 효과를 검증하기 위해 QEC를 포함한 프로토 타입 쿼터 레이트 송신기를 65nm CMOS의 다른 칩으로 제작하였다. QEC를 적용한 실험 결과, 송신기의 출력 위상 오류가 0.8ps의 잔류 오류로 감소하고, 출력 데이터 눈의 폭과 높이가 12.8Gbps의 데이터 속도에서 각각 84 %와 61 % 개선되었음을 보여준다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.1.1 HEAVY LOAD C/A CHANNEL 5 1.1.2 QUARTER-RATE ARCHITECTURE IN DQ TRANSMITTER 7 1.1.3 SUMMARY 8 1.2 THESIS ORGANIZATION 10 CHAPTER 2 ARCHITECTURE 11 2.1 MDS DIMM STRUCTURE 11 2.2 MDS CONTROLLER 15 2.3 MDS CONTROLLER PHY 17 2.3.1 INITIALIZATION SEQUENCE 20 2.3.2 LINK TRAINING FINITE-STATE MACHINE 23 2.3.3 POWER DOWN MODE 28 CHAPTER 3 PULSE-BASED FEED-FORWARD EQUALIZER 29 3.1 COMMAND/ADDRESS CHANNEL 29 3.2 COMMAND/ADDRESS TRANSMITTER 33 3.3 PULSE-BASED FEED-FORWARD EQUALIZER 35 CHAPTER 4 CIRCUIT IMPLEMENTATION 39 4.1 BUILDING BLOCKS 39 4.1.1 ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL) 39 4.1.2 ALL-DIGITAL DELAY-LOCKED LOOP (ADDLL) 44 4.1.3 GLITCH-FREE DCDL CONTROL 47 4.1.4 DUTY-CYCLE CORRECTOR (DCC) 50 4.1.5 DQ/DQS TRANSMITTER 52 4.1.6 DQ/DQS RECEIVER 54 4.1.7 ZQ CALIBRATION 56 4.2 MODELING AND VERIFICATION OF LINK TRAINING 59 4.3 BUILT-IN SELF-TEST CIRCUITS 66 CHAPTER 5 QUADRATURE ERROR CORRECTOR USING REPLICA SERIALIZERS AND PULSE-SHRINKING DELAY LINES 69 5.1 PHASE CORRECTION USING REPLICA SERIALIZERS AND PULSE-SHRINKING UNITS 69 5.2 OVERALL QEC ARCHITECTURE AND ITS OPERATION 71 5.3 FINE DELAY UNIT IN THE PSDL 76 CHAPTER 6 EXPERIMENTAL RESULTS 78 6.1 CONTROLLER PHY 78 6.2 PROTOTYPE QEC 88 CHAPTER 7 CONCLUSION 94 BIBLIOGRAPHY 96Docto

Radiation Hardened by Design Methodologies for Soft-Error Mitigated Digital Architectures

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

PAM4-바이너리 브리지 칩용 PAM4 트랜스미터 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.고성능 컴퓨팅 시스템, 대용량의 데이터 센터, AI 기술의 발전으로 인해 유선 통신의 대역폭 요구 수준은 기하급수적으로 증가하고 있다. 그러나 I/O 회로의 핀당 대역폭의 향상은 통신 채널의 다양한 한계로 인해 어려움을 겪고 있다. 이는 차세대 DRAM 분야에서도 예외는 아니다. 핀당 데이터 전송 속도를 증가시키는 연구 방향에서는 어느 정도 한계에 봉착하면서 최근에는 High Bandwidth Memory (HBM)와 같이 핀의 개수를 급격히 늘려서 대역폭을 증가시키는 기술도 발전하고 있다. 다른 접근 방식 중 한가지가 다중 레벨 신호 방식이다. 기존의 Non-Return-to-Zero (NRZ) 신호 대신에 다중 레벨 신호 방식을 이용하면 동일한 Nyquist 주파수에서 데이터 속도를 높일 수 있고 이는 DRAM의 차세대 고대역폭 I/O 인터페이스에 좋은 솔루션이 될 수 있으며 현재까지는 4레벨 펄스 진폭 변조 방식 (PAM-4)이 널리 채택되어 있다. 하지만 현재 PAM-4 방식 DRAM이 양산 단계가 아니기 때문에 PAM-4 전용 Memory Tester가 없는 상황이다. 본 논문에서는 차세대 메모리 테스트를 위한 32 Gb/s PAM4 바이너리 브리지에서의 트랜스미터를 제안한다. NRZ 테스터에서 브리지로 전송된 저속 데이터는 고속 PAM4 데이터로 변환되어 메모리로 전달된다. 접지 종단 PAM4 드라이버는 2-탭 피드포워드 이퀄라이저로 출력 전류를 제어하여 0.95의 레벨 불일치 비율 (RLM)을 달성함으로써 단일 종단 출력을 제공한다. 40 nm CMOS 기술로 제작된 브리지 트랜스미터는 0.57 mm2의 활성 영역을 차지하고 102.1 mW의 전력을 소모한다.With the advancement of high-performance computing systems, large-capacity data centers, and AI technologies, the level of bandwidth demand for wired communication is increasing exponentially. However, the improvement of the bandwidth per pin in the I/O circuit compared to the required bandwidth level is difficult due to various limitations of the transmission channel. This is no exception in the next generation of DRAM. While facing limitations from the perspective of research that increases data transmission speed per pin, technologies that increase I/O bandwidth by rapidly increasing the number of pins, such as High Bandwidth Memory (HBM), have also recently developed. One of the other approaches is a multi-level signaling method. Using a multi-level signaling method instead of a conventional Non-Return-to-Zero (NRZ) signal can increase data speed at the same Nyquist frequency, which can be a good solution for the next-generation high-bandwidth I/O interface of DRAM, and so far, a four-level Pulse Amplitude Modulation (PAM-4) has been widely adopted. However, since PAM4 DRAM is not in the mass production stage yet, there is no memory tester dedicated to PAM4 signaling. This paper proposes a transmitter block on a 32 Gb/s PAM4 binary bridge for next-generation memory testing. The low-speed data transmitted from the NRZ tester to the bridge is converted into high-speed PAM4 data through half-rate clock control and transferred to the memory. The ground termination PAM4 driver provides a single-ended output by controlling the output current with a two-tap feed forward equalizer to achieve a Level separation Mismatch Ratio (RLM) of 0.95. Bridge transmitter manufactured with 40 nm CMOS technology occupies an active area of 0.57 mm2 and consumes 102.1 mW of power.ABSTRACT I CONTENTS Ⅲ LIST OF FIGURES Ⅴ LIST OF TABLES Ⅶ CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 OVERVIEW 5 2.2 BASIC OF MULTI LEVEL SIGNALING 7 2.3 NECESSITY OF PAM4-BINARY BRIDGE 11 CHAPTER 3 DESIGN OF PAM4 TRANSMITTER FOR PAM4-BINARY BRIDGE 14 3.1 DESIGN CONSIDERATION 14 3.2 OVERALL ARCHITECTURE 17 3.3 CIRCUIT IMPLEMENTATION 19 3.3.1 CLOCK GENERATOR 19 3.3.2 PARALLEL PRBS GENERATOR 23 3.3.3 DATA ALIGN / GRAY CODE ENDCODER 26 3.3.4 FFE CONTROL/ SERIALIZER 30 3.3.5 PAM4 DRIVER 33 CHAPTER 4 MEASUREMENT RESULTS 38 4.1 CHIP PHOTOMICROGRAPH 38 4.2 MEASUREMENT SETUP 39 4.3 MEASUREMENT RESULTS 40 4.4 PERFORMANCE SUMMARY 42 CHAPTER 5 CONCLUSION 46 BIBLIOGRAPHY 47 초 록 50석

Recent advances in the hardware architecture of flat display devices

Thesis (Master)--Izmir Institute of Technology, Electronics and Communication Engineering, Izmir, 2007Includes bibliographical References (leaves: 115-117)Text in English; Abstract: Turkish and Englishxiii, 133 leavesThesis will describe processing board hardware design for flat panel displays with integrated digital reception, the design challenges in flat panel displays with integrated digital reception explained with details. Thesis also includes brief explanation of flat panel technology and processing blocks. Explanations of building blocks of TV and flat panel displays are given before design stage for better understanding of design stage. Hardware design stage of processing board is investigated in two major steps, schematic design and layout design. First step of the schematic design is system level block diagram design. Schematic diagram is the detailed application level hardware design and layout is the implementation level of the design. System level, application level and implementation level hardware design of the TV processing board is described with details in thesis. Design challenges, considerations and solutions are defined in advance for flat panel displays

Architectures and Algorithms for the Signal Processing of Advanced MIMO Radar Systems

This thesis focuses on the research, development and implementation of novel concepts, architectures, demonstrator systems and algorithms for the signal processing of advanced Multiple Input Multiple Output (MIMO) radar systems. The key concept is to address compact system, which have high resolutions and are able to perform a fast radar signal processing, three-dimensional (3D), and four-dimensional (4D) beamforming for radar image generation and target estimation. The idea is to obtain a complete sensing of range, Azimuth and elevation (additionally Doppler as the fourth dimension) from the targets in the radar captures. The radar technology investigated, aims at addressing sev- eral civil and military applications, such as surveillance and detection of targets, both air and ground based, and situational awareness, both in cars and in flying platforms, from helicopters, to Unmanned Aerial Vehicles (UAV) and air-taxis. Several major topics have been targeted. The development of complete systems and innovative FPGA, ARM and software based digital architectures for 3D imaging MIMO radars, which operate in both Time Division Multiplexing (TDM) and Frequency Divi- sion Multiplexing (FDM) modes, with Frequency Modulated Continuous Wave (FMCW) and Orthogonal Frequency Division Multiplexing (OFDM) signals, respectively. The de- velopment of real-time radar signal processing, beamforming and Direction-Of-Arrival (DOA) algorithms for target detection, with particular focus on FFT based, hardware implementable techniques. The study and implementation of advanced system concepts, parametrisation and simulation of next generation real-time digital radars (e.g. OFDM based). The design and development of novel constant envelope orthogonal waveforms for real-time 3D OFDM MIMO radar systems. The MIMO architectures presented in this thesis are a collection of system concepts, de- sign and simulations, as well as complete radar demonstrators systems, with indoor and outdoor measurements. Several of the results shown, come in the form of radar images which have been captured in field-test, in different scenarios, which aid in showing the proper functionality of the systems. The research activities for this thesis, have been carried out on the premises of Air- bus, based in Munich (Germany), as part of a Ph.D. candidate joint program between Airbus and the Polytechnic Department of Engineering and Architecture (Dipartimento Politecnico di Ingegneria e Architettura), of the University of Udine, based in Udine (Italy).Questa tesi si concentra sulla ricerca, lo sviluppo e l\u2019implementazione di nuovi concetti, architetture, sistemi dimostrativi e algoritmi per l\u2019elaborazione dei segnali in sistemi radar avanzati, basati su tecnologia Multiple Input Multiple Output (MIMO). Il con- cetto chiave `e quello di ottenere sistemi compatti, dalle elevate risoluzioni e in grado di eseguire un\u2019elaborazione del segnale radar veloce, un beam-forming tri-dimensionale (3D) e quadri-dimensionale (4D) per la generazione di immagini radar e la stima delle informazioni dei bersagli, detti target. L\u2019idea `e di ottenere una stima completa, che includa la distanza, l\u2019Azimuth e l\u2019elevazione (addizionalmente Doppler come quarta di- mensione) dai target nelle acquisizioni radar. La tecnologia radar indagata ha lo scopo di affrontare diverse applicazioni civili e militari, come la sorveglianza e la rilevazione di targets, sia a livello aereo che a terra, e la consapevolezza situazionale, sia nelle auto che nelle piattaforme di volo, dagli elicotteri, ai Unmanned Aerial Vehicels (UAV) e taxi volanti (air-taxis). Le tematiche affrontante sono molte. Lo sviluppo di sistemi completi e di architetture digitali innovative, basate su tecnologia FPGA, ARM e software, per radar 3D MIMO, che operano in modalit`a Multiplexing Time Division Multiplexing (TDM) e Multiplexing Frequency Diversion (FDM), con segnali di tipo FMCW (Frequency Modulated Contin- uous Wave) e Orthogonal Frequency Division Multiplexing (OFDM), rispettivamente. Lo sviluppo di tecniche di elaborazione del segnale radar in tempo reale, algoritmi di beam-forming e di stima della direzione di arrivo, Direction-Of-Arrival (DOA), dei seg- nali radar, per il rilevamento dei target, con particolare attenzione a processi basati su trasformate di Fourier (FFT). Lo studio e l\u2019implementazione di concetti di sistema avan- zati, parametrizzazione e simulazione di radar digitali di prossima generazione, capaci di operare in tempo reale (ad esempio basati su architetture OFDM). Progettazione e sviluppo di nuove forme d\u2019onda ortogonali ad inviluppo costante per sistemi radar 3D di tipo OFDM MIMO, operanti in tempo reale. Le attivit`a di ricerca di questa tesi sono state svolte presso la compagnia Airbus, con sede a Monaco di Baviera (Germania), nell\u2019ambito di un programma di dottorato, svoltosi in maniera congiunta tra Airbus ed il Dipartimento Politecnico di Ingegneria e Architettura dell\u2019Universit`a di Udine, con sede a Udine

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

Replacing full custom DAQ test system by COTS DAQ components on example of ATLAS SCT readout

A test system developed for ABCN-25 for ATLAS Inner Detector Upgrade is presented. The system is based on commercial off the shelf DAQ components by National Instruments and foreseen to aid in chip characterization and hybrid/module development complementing full custom VME based setups. The key differences from the point of software development are presented, together with guidelines for developing high performance LabVIEW code. Some real-world benchmarks will also be presented together with chip test results. The presented tests show good agreement of test results between the test setups used in different sites, as well as agreement with design specifications of the chip

Analysis and design of power delivery networks exploiting simulation tools and numerical optimization techniques

A higher performance of computing systems is being demanded year after year, driving the digital industry to fiercely compete for offering the fastest computer system at the lowest cost. In addition, as computing system performance is growing, power delivery networks (PDN) and power integrity (PI) designs are getting increasingly more relevance due to the faster speeds and more parallelism required to obtain the required performance growth. The largest data throughput at the lowest power consumption is a common goal for most of the commercial computing systems. As a consequence of this performance growth and power delivery tradeoffs, the complexity involved in analyzing and designing PDN in digital systems is being increased. This complexity drives longer design cycle times when using traditional design tools. For this reason, the need of using more efficient design methods is getting more relevance in order to keep designing and launching products in a faster manner to the market. This trend pushes PDN designers to look for methodologies to simplify analysis and reduce design cycle times. The main objective for this Master’s thesis is to propose alternative methods by exploiting reliable simulation approaches and efficient numerical optimization techniques to analyze and design PDN to ensure power integrity. This thesis explores the use of circuital models and electromagnetic (EM) field solvers in combination with numerical optimization methods, including parameter extraction (PE) formulations. It also establishes a sound basis for using space mapping (SM) methodologies in future developments, in a way that we exploit the advantages of the most accurate and powerful models, such as 3D full-wave EM simulators, but conserving the simplicity and low computational resourcing of the analytical, circuital, and empirical models