The analysis and modeling of fine pitch laminate interconnect in response to large energy fault transients

In embedded applications, the miniaturization of circuitry and functionality provides many benefits to both the producer and consumer. However, the benefits gained from miniaturization is not without penalty, as the environmental influences may be great enough to introduce system failures in new or different modes and effects;Of particular interest within this research is the effect of fault transients in reduced geometries of printed circuit card interconnect, commonly referred to as fine pitch laminate interconnect. Whereas larger geometries of conductor trace width and spacing may have been immune to circuit failure at a given fault input, the reduction of the trace geometry may introduce failures as the insulating effect of the dielectric is compromised to the point where arcing occurs;To address this concern, a circuit card was designed with fine pitch laminate features in microstrip, embedded microstrip, and stripline constructions. Various trace widths and separations were tested for structural integrity (presence of arcing or fusing) at voltage extremes defined in avionics standard. The specific trace widths in the test were 4 mils, 6 mils, 8 mils, and 12 mils, with the trace separation in each case equal to the trace widths. The results of the tests and methods to artificially improve the integrity of the interconnect are documented, providing a clear region of reliable operation to the designers and the engineering community;Finally, the construction of the interconnect and the results from the test were combined to create an empirical model for circuit analysis. Created for the Saber simulator, but readily adaptable to Spice, this model will describe high-speed operation of a propagating signal before breakdown, and uses data from the experiment to calculate threshold values for the arcing breakdown. The values for the breakdown voltages are correlated to the experimental data using statistical methods of weighted linear regression and hypothesis testing

Stochastic Testing Simulator for Integrated Circuits and MEMS: Hierarchical and Sparse Techniques

Process variations are a major concern in today's chip design since they can significantly degrade chip performance. To predict such degradation, existing circuit and MEMS simulators rely on Monte Carlo algorithms, which are typically too slow. Therefore, novel fast stochastic simulators are highly desired. This paper first reviews our recently developed stochastic testing simulator that can achieve speedup factors of hundreds to thousands over Monte Carlo. Then, we develop a fast hierarchical stochastic spectral simulator to simulate a complex circuit or system consisting of several blocks. We further present a fast simulation approach based on anchored ANOVA (analysis of variance) for some design problems with many process variations. This approach can reduce the simulation cost and can identify which variation sources have strong impacts on the circuit's performance. The simulation results of some circuit and MEMS examples are reported to show the effectiveness of our simulatorComment: Accepted to IEEE Custom Integrated Circuits Conference in June 2014. arXiv admin note: text overlap with arXiv:1407.302

Computational Prototyping Tools and Techniques

Contains reports on five research projects.Industry Consortium (Mobil, Statoil, DNV Software, Shell, OTRC, Petrobras, NorskHydro, Exxon, Chevron, SAGA, NSWC)U.S. Navy - Office of Naval ResearchAnalog DevicesDefense Advanced Research Projects Agency Contract J-FBI-95-215Cadence Design SystemsHarris SemiconductorMAFET ConsortiumMotorola SemiconductorDefense Advanced Research Projects AgencyMultiuniversity Research InitiativeSemiconductor Research CorporationIBM Corporatio

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours 10^5X acceleration under the 150C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs

Thermal Analysis of VLSI System: A Simulation Study

Smaller size of Very Large Scale Integrated (VLSI) System nowadays increases the on chip power densities causing the rise of temperature in the system. The high temperature produced will eventually affects the clock frequency of the system and changes the timing setup of the component. These lead to lowering the performance and reliability of the system. Due to the negative effects of the high temperature, designers have to determine the thermal profile of the systems in order to understand the temperature distribution, the leakage reduction and estimate the power distribution of the system. This research focuses on analyzing the thermal profile of a VLSI system under steady state condition using numerical techniques and simulation. For the numerical techniques, the governing heat equation for a two-dimensional (2D) model was solved using Finite Difference Method (FDM), Gauss-Seidel (GS) and Successive Over Relaxation (SOR) methods. Simulation based on ANSYS simulator has been conducted for validation purpose. Most commonly material used in VLSI system which is Silicon (Si) is tested under adiabatic condition. The results for numerical techniques and the simulation are compared. SOR method shows better results in terms of number of iterations and the computational time compared to GS method in solving the governing heat equation. Both methods have the same maximum temperature and these temperatures are comparable with the result obtained by using ANSYS

Transient simulation of complex electronic circuits and systems operating at ultra high frequencies

The electronics industry worldwide faces increasingly difficult challenges in a bid to produce ultra-fast, reliable and inexpensive electronic devices. Electronic manufacturers rely on the Electronic Design Automation (EDA) industry to produce consistent Computer A id e d Design (CAD) simulation tools that w ill enable the design of new high-performance integrated circuits (IC), the key component of a modem electronic device. However, the continuing trend towards increasing operational frequencies and shrinking device sizes raises the question of the capability of existing circuit simulators to accurately and efficiently estimate circuit behaviour. The principle objective of this thesis is to advance the state-of-art in the transient simulation of complex electronic circuits and systems operating at ultra high frequencies. Given a set of excitations and initial conditions, the research problem involves the determination of the transient response o f a high-frequency complex electronic system consisting of linear (interconnects) and non-linear (discrete elements) parts with greatly improved efficien cy compared to existing methods and with the potential for very high accuracy in a way that permits an effective trade-off between accuracy and computational complexity. High-frequency interconnect effects are a major cause of the signal degradation encountered b y a signal propagating through linear interconnect networks in the modem IC. Therefore, the development of an interconnect model that can accurately and efficiently take into account frequency-dependent parameters of modem non-uniform interconnect is of paramount importance for state-of-art circuit simulators. Analytical models and models based on a set of tabulated data are investigated in this thesis. Two novel, h igh ly accurate and efficient interconnect simulation techniques are developed. These techniques combine model order reduction methods with either an analytical resonant model or an interconnect model generated from frequency-dependent sparameters derived from measurements or rigorous full-wave simulation. The latter part o f the thesis is concerned with envelope simulation. The complex mixture of profoundly different analog/digital parts in a modern IC gives rise to multitime signals, where a fast changing signal arising from the digital section is modulated by a slower-changing envelope signal related to the analog part. A transient analysis of such a circuit is in general very time-consuming. Therefore, specialised methods that take into account the multi-time nature o f the signal are required. To address this issue, a novel envelope simulation technique is developed. This technique combines a wavelet-based collocation method with a multi-time approach to result in a novel simulation technique that enables the desired trade-off between the required accuracy and computational efficiency in a simple and intuitive way. Furthermore, this new technique has the potential to greatly reduce the overall design cycle

Modeling of diffusional creep and stress relaxation in copper grains during manufacturing of microelectronic integrated circuits

The finite element technique was developed to study diffusional creep and stress relaxation in Cu grains with several atomic monolayers thick grain boundary region of enhanced diffusivity. The model was motivated by the need to study nanoscale back-end interconnect structures of microelectronic circuits. These structures have the length scale that does not conform to the assumptions of classical dimensional theories of diffusional creep. Both diffusion and elasticity governing equations are considered in the coupled formulation of mass flow and stress analysis. Vacancy concentration field in the grains subjected to external load is coupled to stress field through diffusional creep strains. The formulation has been implemented in the commercially available finite element software package MSC.Marc. We validated the model for the case of stress relaxation in one-dimensional grain array by comparing the finite element simulations to the predictions of classical Nabarro-Herring and Coble theories. The numerical results show good correspondence to analytical predictions, suggesting that this model may be used to predict diffusive stress relaxation in more advanced systems of practical importance, such as Cu interconnects at elevated temperatures. We have used our model to study the effect of grain size on creep rate in a polycrystal under external load. The approach has been applied to study the stress relaxation in a typical Cu-Ta-dielectric structure subjected to thermal loads. To improve the computational efficiency of the diffusional creep modeling, we developed the numerical technique of equivalent viscoplastic finite elements. This approach was found to improve the computational efficiency by reducing the coupled elasticity-mass flow problem to the equivalent mechanical creep analysis. The predictions of the equivalent element viscoplastic model showed good correspondence to the stress relaxation results obtained with coupled elasticity-mass flow FEA approach