Trends and Challenges in CMOS Design for Emerging 60 GHz WPAN Applications

International audienceThe extensive growth of wireless communications industry is creating a big market opportunity. Wireless operators are currently searching for new solutions which would be implemented into the existing wireless communication networks to provide the broader bandwidth, the better quality and new value-added services. In the last decade, most commercial efforts were focused on the 1-10 GHz spectrum for voice and data applications for mobile phones and portable computers (Niknejad & Hashemi, 2008). Nowadays, the interest is growing in applications that use high rate wireless communications. Multigigabit- per-second communication requires a very large bandwidth. The Ultra-Wide Band (UWB) technology was basically used for this issue. However, this technology has some shortcomings including problems with interference and a limited data rate. Furthermore, the 3-5 GHz spectrum is relatively crowded with many interferers appearing in the WiFi bands (Niknejad & Hashemi, 2008). The use of millimeter wave frequency band is considered the most promising technology for broadband wireless. In 2001, the Federal Communications Commission (FCC) released a set of rules governing the use of spectrum between 57 and 66 GHz (Baldwin, 2007). Hence, a large bandwidth coupled with high allowable transmit power equals high possible data rates. Traditionally the implementation of 60 GHz radio technology required expensive technologies based on III-V compound semiconductors such as InP and GaAs (Smulders et al., 2007). The rapid progress of CMOS technology has enabled its application in millimeter wave applications. Currently, the transistors became small enough, consequently fast enough. As a result, the CMOS technology has become one of the most attractive choices in implementing 60 GHz radio due to its low cost and high level of integration (Doan et al., 2005). Despite the advantages of CMOS technology, the design of 60 GHz CMOS transceiver exhibits several challenges and difficulties that the designers must overcome. This chapter aims to explore the potential of the 60 GHz band in the use for emergent generation multi-gigabit wireless applications. The chapter presents a quick overview of the state-of-the-art of 60 GHz radio technology and its potentials to provide for high data rate and short range wireless communications. The chapter is organized as follows. Section 2 presents an overview about 60 GHz band. The advantages are presented to highlight the performance characteristics of this band. The opportunities of the physical layer of the IEEE 802.15.3c standard for emerging WPAN applications are discussed in section 3. The tremendous opportunities available with CMOS technology in the design of 60 GHz radio is discussed in section 4. Section 5 shows an example of 60 GHz radio system link. Some challenges and trade-offs on the design issues of circuits and systems for 60 GHz band are reported in section 6. Finally, section 7 presents the conclusion and some perspectives on future directions

Oscillateur de puissance en ondes millimétriques

Ce travail porte sur l'étude d'un oscillateur de puissance contrôlé en tension en ondes millimétriques. L'objectif de la thèse est de concevoir cet oscillateur pour la bande de fréquence utilisée dans les standards IEEE 802.15.3c, IEEE 802.11ad et ECMA TC48, à savoir 56GHz-65GHz. Le principe de l'oscillateur de puissance est développé autour d'un amplificateur de puissance rebouclé pour engendrer un système oscillant. L'amplificateur de puissance développé est un amplicateur à deux étages. Celui de puissance est de classe E et le driver est de classe F. La boucle de retour est basée sur un vecteur-modulateur. Les circuits ont été fabriqués en technologie CMOS 65nm de STMicroelectronics.This PhD thesis deals with a Power Voltage Controlled Oscillator (VCO) in millimeter waves. The aim is to design this Power VCO in the frequency band used in the standards IEEE 802.15.3c, IEEE 802.11ad and ECMA TC48, meaning from 56GHz to 65GHz. The principle of this oscillator is developed around a power amplifier in a loop, generating an oscillating system. The power amplifier is developed in a two-stage topology. The power stage is composed with a 60GHz class E cascoded amplifier and the driver stage is composed of a 60GHz class F amplifier. The feedback of the loop is based on a vector-modulator. The circuits have been realised in 65nm CMOS technology from STMicroelectronics.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Ultra high data rate CMOS FEs

The availability of numerous mm-wave frequency bands for wireless communication has motived the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performaning measurements using on-wafer probing at 60GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitiv to the effective length and bending of the interfaces. This paper presents different 60GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, A Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60GHZ integrated components and systems in the main stream CMOS technology

Ultra high data rate CMOS front ends

The availability of numerous mm-wave frequency bands for wireless communication has motivated the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performing measurements using on-wafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the interfaces. This paper presents different 60 GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, a Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60 GHZ integrated components and systems in the main stream CMOS technology

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

The Design and Linearization of 60GHz Injection Locked Power Amplifier

The RF power amplifier is one of the most critical blocks of transceivers, as it is expected to provide a suitable output power with high gain, efficiency and linearity. In this paper, a 60-GHz power amplifier based on an injection locked structure is demonstrated in a standard 65 CMOS technology. The PA core consists of a cross-coupled pair of NMOS transistors with an NMOS current source. This structure can achieve large output power and high PAE, but with poor linearity performance. In order to improve the linearity, several linearization techniques are investigated, including adaptive biasing and predistortion. The results show that the adaptive biasing technique can enlarge the linear operation region, but results in poor AM-PM performance. By instead using the predistortion technique, the AM-PM performance can be improved, but the linear region only extends slightly. Considering theses two techniques different advantages, we combine them together to improve not only the linear region but also the AM-PM performance. Finally, a common source amplifier is added as the first stage. With proper bias, the linear operation region is then effectively extended by 7.3 dB. This two stage power amplifier achieves large output power, high linearity and high PAE simultaneously. It delivers a gain of 20dB, a Psat of 16.3dBm, a P1dB of 15.41dBm, and a PAE of 30%.Since the invention of radio-frequency (RF) wireless communication more than 100 years ago, mobile phones and other wireless communications products for civilian consumption have developed rapidly. Nowadays, the demand for larger high data rate and capacities is rising sharply. The traditional wireless bandwidth is no longer able to meet some high-rate applications requirement. However, 60GHz wireless communication system is our solution, and up to 7 GHz unlicensed wide band around 60GHz is open to use across much of the world. Furthermore, the power amplifier (PA) is a critical part of any transmitter to convert the signal to higher power and drive the antenna. For power amplifiers, efficiency and linearity are most important. Power amplifiers with low efficiency will result in high level of heat dissipation. Linearity is a measure of the signal distortion, which consists of gain compression (AM-AM distortion) and phase distortion (AM-PM distortion). In this thesis work, an injection locked power amplifier is used to reduce the input driving requirements and improve the efficiency. Simulations have been performed for implementation in 65nm standard CMOS, which is a low-cost technology for fabrication of integrated circuits (chips). The injection locked technique means that a self-oscillating circuit is forced to run at the same frequency as the input signal. Furthermore, an integrated balun is added to transfer between single-ended and differential signals. The results show that this PA can achieve high efficiency but with poor linearity performance. In order to improve the linearity, different linearization techniques are investigated, including adaptive biasing and predistortion. Adaptive biasing is a feedback technique. At high output levels, the power amplifier has less gain, which leads to signal distortion. The adaptive biasing unit can sense the output power in real time and adjust the bias. The bias is then increased at increased output power in order to restore the power gain at high output levels. Predistortion is another linearization technique. A predistorter, which has a gain expansion characteristic, is then introduced before the PA to compensate for its gain reduction. Then, considering the advantages of these two linearization techniques, we combine them together to achieve even better results. Finally, a two-stage power amplifier is proposed by adding a common source amplifier as the first stage. The first stage can also produce a gain boost at the high output levels, and this expansion gain can be made to match the second-stage gain reduction very well. The simulation results show that the amplifier can achieve high linearity and efficiency at the same time

Millimeter-scale RF Integrated Circuits and Antennas for Energy-efficient Wireless Sensor Nodes

Recently there has been increased demand for a millimeter-scale wireless sensor node for applications such as biomedical devices, defense, and surveillance. This form-factor is driven by a desire to be vanishingly small, injectable through a needle, or implantable through a minimally-invasive surgical procedure. Wireless communication is a necessity, but there are several challenges at the millimeter-scale wireless sensor node. One of the main challenges is external components like crystal reference and antenna become the bottleneck of realizing the mm-scale wireless sensor node device. A second challenge is power consumption of the electronics. At mm-scale, the micro-battery has limited capacity and small peak current. Moreover, the RF front-end circuits that operates at the highest frequency in the system will consume most of the power from the battery. Finally, as node volume reduces, there is a challenge of integrating the entire system together, in particular for the RF performance, because all components, including the battery and ICs, need to be placed in close proximity of the antenna. This research explores ways to implement low-power integrated circuits in an energy-constrained and volume constrained application. Three different prototypes are mainly conducted in the proposal. The first is a fully-encapsulated, autonomous, complete wireless sensor node with UWB transmitter in 10.6mm3 volume. It is the first time to demonstrate a full and stand-alone wireless sensing functionality with such a tiny integrated system. The second prototype is a low power GPS front-end receiver that supports burst-mode. A double super-heterodyne topology enables the reception of the three public GPS bands, L1, L2 and L5 simultaneously. The third prototype is an integrated rectangular slot loop antenna in a standard 0.13-μm BiCMOS technology. The antenna is efficiently designed to cover the bandwidth at 60 GHz band and easily satisfy the metal density rules and can be integrated with other circuitry in a standard process.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/143972/1/hskims_1.pd