Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Energy Efficient Pipeline ADCs Using Ring Amplifiers

Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency. The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversion∙step. The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion∙step and 174.9 dB, respectively. Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

Design of Power Management Integrated Circuits and High-Performance ADCs

A battery-powered system has widely expanded its applications to implantable medical devices (IMDs) and portable electronic devices. Since portable devices or IMDs operate in the energy-constrained environment, their low-power operations in combination with efficiently sourcing energy to them are key problems to extend device life. This research proposes novel circuit techniques for two essential functions of a power receiving unit (PRU) in the energy-constrained environment, which are power management and signal processing. The first part of this dissertation discusses power management integrated circuits for a PRU. From a power management perspective, the most critical two circuit blocks are a front-end rectifier and a battery charger. The front-end CMOS active rectifier converts transmitted AC power into DC power. High power conversion efficiency (PCE) is required to reduce power loss during the power transfer, and high voltage conversion ratio (VCR) is required for the rectifier to enable low-voltage operations. The proposed 13.56-MHz CMOS active rectifier presents low-power circuit techniques for comparators and controllers to reduce increasing power loss of an active diode with offset/delay calibration. It is implemented with 5-V devices of a 0.35 µm CMOS process to support high voltage. A peak PCE of 89.0%, a peak VCR of 90.1%, and a maximum output power of 126.7 mW are measured for 200Ω loading. The linear battery charger stores the converted DC power into a battery. Since even small power saving can be enough to run the low-power PRU, a battery charger with low IvQ is desirable. The presented battery charger is based on a single amplifier for regulation and the charging phase transition from the constant-current (CC) phase to the constant-voltage (CV) phase. The proposed unified amplifier is based on stacked differential pairs which share the bias current. Its current-steering property removes multiple amplifiers for regulation and the CC-CV transition, and achieves high unity-gain loop bandwidth for fast regulation. The charger with the maximum charging current of 25 mA is implemented in 0.35 µm CMOS. A peak charger efficiency of 94% and average charger efficiency of 88% are achieved with an 80-mAh Li-ion polymer battery. The second part of this dissertation focuses on analog-to-digital converters (ADCs). From a signal processing perspective, an ADC is one of the most important circuit blocks in the PRU. Hence, an energy-efficient ADC is essential in the energy-constrained environment. A pipelined successive approximation register (SAR) ADC has good energy efficiency in a design space of moderate-to-high speeds and resolutions. Process-Voltage-Temperature variations of a dynamic amplifier in the pipelined-SAR ADC is a key design issue. This research presents two dynamic amplifier architectures for temperature compensation. One is based on a voltage-to-time converter (VTC) and a time-to-voltage converter (TVC), and the other is based on a temperature-dependent common-mode detector. The former amplifier is adopted in a 13-bit 10-50 MS/s subranging pipelined-SAR ADC fabricated in 0.13-µm CMOS. The ADC can operate under the power supply voltage of 0.8-1.2 V. Figure-of-Merits (FoMs) of 4-11.3 fJ/conversion-step are achieved. The latter amplifier is also implemented in 0.13-µm CMOS, consuming 0.11 mW at 50 MS/s. Its measured gain variation is 2.1% across the temperature range of -20°C to 85 °C