An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side only, can efficiently remove crosstalk patterns in straight channels as well as boards with reflections due to via stubs. An eight-lane single-ended RX has been manufactured in 32-nm SOI CMOS to validate our findings. A CTLE and eight-tap decision feedback equalizer equalize the channel without transmitter feedforward equalizer. A continuous time crosstalk canceller reduces precursors by nearest neighbors, while the residual postcursors from all aggressors are suppressed by direct feedback 7x8-tap decision-feedback crosstalk canceller (DFXC). Measurements with flip-chip packaged RX show that the RX macro can equalize both a 30-dB insertion loss single-ended channel with 0-dB signal-to-crosstalk at Nyquist and a channel with 28-dB attenuation with the signal-to-crosstalk ratio of 6 dB combined with reflections due to via stubs. The RX operates up to 7 Gb/s/pin with PRBS11 data at bit error rate (BER) <10⁻¹², and occupies 300x350 μm² with an energy efficiency of 5.9 mW/Gb/s from 1-V supply

Design Techniques for High Performance Serial Link Transceivers

Increasing data rates over electrical channels with significant frequency-dependent loss is difficult due to excessive inter-symbol interference (ISI). In order to achieve sufficient link margins at high rates, I/O system designers implement equalization in the transmitters and are motivated to consider more spectrally-efficient modulation formats relative to the common PAM-2 scheme, such as PAM-4 and duobinary. The first work, reviews when to consider PAM-4 and duobinary formats, as the modulation scheme which yields the highest system margins at a given data rate is a function of the channel loss profile, and presents a 20Gb/s triple-mode transmitter capable of efficiently implementing these three modulation schemes and three-tap feedforward equalization. A statistical link modeling tool, which models ISI, crosstalk, random noise, and timing jitter, is developed to compare the three common modulation formats operating on electrical backplane channel models. In order to improve duobinary modulation efficiency, a low-power quarter-rate duobinary precoder circuit is proposed which provides significant timing margin improvement relative to full-rate precoders. Also as serial I/O data rates scale above 10 Gb/s, crosstalk between neighboring channels degrades system bit-error rate (BER) performance. The next work presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an ondie sign-sign least-mean-square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. In conclusion, the proposed architectures in the transmitter side and receiver side together are to be good solution in the high speed I/O serial links to improve the performance by overcome the physical channel loss and adjacent channel noise as the system becomes complicated

Modeling and Linearization of MIMO RF Transmitters

Multiple-input multiple-output (MIMO) technology will continue to play a vital role in next-generation wireless systems, e.g., the fifth-generation wireless networks (5G). Large-scale antenna arrays (also called massive MIMO) seem to be the most promising physical layer solution for meeting the ever-growing demand for high spectral efficiency. Large-scale MIMO arrays are typically deployed with high integration and using low-cost components. Hence, they are prone to different hardware impairments such as crosstalk between the transmit antennas and power amplifier (PA) nonlinearities, which distort the transmitted signal. To avert the performance degradation due to these impairments, it is essential to have mechanisms for predicting the output of the MIMO arrays. Such prediction mechanisms are mandatory for performance evaluation and, more importantly, for the adoption of proper compensation techniques such as digital predistortion (DPD) schemes. This has stirred a considerable amount of interest among researchers to develop new hardware and signal processing solutions to address the requirements of large-scale MIMO systems. In the context of MIMO systems, one particular problem is that the hardware cost and complexity scale up with the increase of the size of the MIMO system. As a result, the MIMO systems tend to be implemented on a chip and are very compact. Reduction of the cost by reducing the bill of material is possible when several components are eliminated. The reuse of already existing hardware is an alternative solution. As a result, such systems are prone to excessive sources of distortion, such as crosstalk. Accordingly, crosstalk in MIMO systems in its simplest form can affect the DPD coefficient estimation scheme. In this thesis, the effect of crosstalk on two main DPD estimation techniques, know as direct learning algorithm (DLA) and indirect learning algorithm (ILA), is studied. The PA behavioral modeling and DPD scheme face several challenges that seek cost-efficient and flexible solutions too. These techniques require constant capture of the PA output feedback signal, which ultimately requires the implementation of a complete transmitter observation receiver (TOR) chain for the individual transmit path. In this thesis, a technique to reuse the receiver path of the MIMO TDD transceiver as a TOR is developed, which is based on over-the-air (OTA) measurements. With these techniques, individual PA behavioral modeling and DPD can be done by utilizing a few receivers of the MIMO TDD system. To use OTA measurements, an on-site antenna calibration scheme is developed to individually estimate the coupling between the transmitter and the receiver antennas. Furthermore, a digital predistortion technique for compensating the nonlinearity of several PAs in phased arrays is presented. The phased array can be a subset of massive MIMO systems, and it uses several antennas to steer the transmitted signal in a particular direction by appropriately assigning the magnitude and the phase of the transmitted signal from each antenna. The particular structure of phased arrays requires the linearization of several PAs with a single DPD. By increasing the number of RF branches and consequently increasing the number of PAs in the phased array, the linearization task becomes challenging. The DPD must be optimized to results in the best overall linear performance of the phased array in the field. The problem of optimized DPD for phased array has not been addressed appropriately in the literature. In this thesis, a DPD technique is developed based on an optimization problem to address the linearization of PAs with high variations. The technique continuously optimizes the DPD coefficients through several iterations considering the effect of each PA simultaneously. Therefore, it results in the best optimized DPD performance for several PAs. Extensive analysis, simulations, and measurement evaluation is carried out as a proof of concept. The different proposed techniques are compared with conventional approaches, and the results are presented. The techniques proposed in this thesis enable cost-efficient and flexible signal processing approaches to facilitate the development of future wireless communication systems

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

Over the past few decades, incessant growth of Internet networking traffic and High-Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends have enabled the semiconductor and microelectronic industry to dramatically scale the bandwidth of high-loss interfaces such as Ethernet, backplane, and Digital Subscriber Line (DSL). The key to achieving higher bandwidth is to employ equalization technique to compensate the channel impairments such as Inter-Symbol Interference (ISI), crosstalk, and environmental noise. Therefore, todayâs advanced input/outputs (I/Os) has been equipped with sophisticated equalization techniques to push beyond the uncompensated bandwidth of the system. To this end, process scaling has continually increased the data processing capability and improved the I/O performance over the last 15 years. However, since the channel bandwidth has not scaled with the same pace, the required signal processing and equalization circuitry becomes more and more complicated. Thereby, the energy efficiency improvements are largely offset by the energy needed to compensate channel impairments. In this design paradigm, re-thinking about the design strategies in order to not only satisfy the bandwidth performance, but also to improve power-performance becomes an important necessity. It is well known in communication theory that coding and signaling schemes have the potential to provide superior performance over band-limited channels. However, the choice of the optimum data communication algorithm should be considered by accounting for the circuit level power-performance trade-offs. In this thesis we have investigated the application of new algorithm and signaling schemes in wireline communications, especially for communication between microprocessors, memories, and peripherals. A new hybrid NRZ/Multi-Tone (NRZ/MT) signaling method has been developed during the course of this research. The system-level and circuit-level analysis, design, and implementation of the proposed signaling method has been performed in the frame of this work, and the silicon measurement results have proved the efficiency and the robustness of the proposed signaling methodology for wireline interfaces. In the first part of this work, a 7.5 Gb/s hybrid NRZ/MT transceiver (TRX) for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel bearing 45 dB loss at 2.5 GHz. The measurement results of the first prototype confirm that NRZ/MT serial data TRX can offer an energy-efficient solution for MDB memory interfaces. Motivated by the satisfying results of the first prototype, in the second phase of this research we have exploited the properties of multi-tone signaling, especially orthogonality among different sub-bands, to reduce the effect of crosstalk in high-dense wireline interconnects. A four-channel transceiver has been implemented in a standard CMOS 40 nm technology in order to demonstrate the performance of NRZ/MT signaling in presence of high channel loss and strong crosstalk noise. The proposed system achieves 1 pJ/bit power efficiency, while communicating over a MDB memory channel at 36 Gb/s aggregate data rate

Learning-Based Hardware Design for Data Acquisition Systems

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conceptually allowing radically new device designs. The mathematical results in classical Compressive Sampling (CS) support the paradigm of Analog-to-Information Conversion (AIC) as a replacement for conventional ADC technologies. The AICs simultaneously perform data acquisition and compression, seeking to directly sample signals for achieving specific tasks as opposed to acquiring a full signal only at the Nyquist rate to throw most of it away via compression. Our contention is that in order for CS to live up its name, both theory and practice must leverage concepts from learning. This work demonstrates our contention in hardware prototypes, with key trade-offs, for two different fields of application as edge and big-data computing. In the framework of edge-data computing, such as wearable and implantable ecosystems, the power budget is defined by the battery capacity, which generally limits the device performance and usability. This is more evident in very challenging field, such as medical monitoring, where high performance requirements are necessary for the device to process the information with high accuracy. Furthermore, in applications like implantable medical monitoring, the system performances have to merge the small area as well as the low-power requirements, in order to facilitate the implant bio-compatibility, avoiding the rejection from the human body. Based on our new mathematical foundations, we built different prototypes to get a neural signal acquisition chip that not only rigorously trades off its area, energy consumption, and the quality of its signal output, but also significantly outperforms the state-of-the-art in all aspects. In the framework of big-data and high-performance computation, such as in high-end servers application, the RF circuits meant to transmit data from chip-to-chip or chip-to-memory are defined by low power requirements, since the heat generated by the integrated circuits is partially distributed by the chip package. Hence, the overall system power budget is defined by its affordable cooling capacity. For this reason, application specific architectures and innovative techniques are used for low-power implementation. In this work, we have developed a single-ended multi-lane receiver for high speed I/O link in servers application. The receiver operates at 7 Gbps by learning inter-symbol interference and electromagnetic coupling noise in chip-to-chip communication systems. A learning-based approach allows a versatile receiver circuit which not only copes with large channel attenuation but also implements novel crosstalk reduction techniques, to allow single-ended multiple lines transmission, without sacrificing its overall bandwidth for a given area within the interconnect's data-path