Ultra-Low-Power Configurable Analog Signal Processor for Wireless Sensors

The demand for on-chip low-power Complementary Metal Oxide Semiconductor (CMOS) analog signal processing has significantly increased in recent years. Digital signal processors continue to shrink in size as transistors half in size every two years. However, digital signal processors (DSP\u27s) notoriously use more power than analog signal processors (APS\u27s). This thesis presents a configurable analog signal processor (CASP) used for wireless sensors. This CASP contains a multitude of processing blocks include the following: low pass filter (LPF), high pass filter (HPF) integrator, differentiator, operational transconductance amplifier (OTA), rectifier with absolute value functionality, and multiplier. Each block uses current-mode processing and operates in the sub-threshold region of operation. Current-mode processing allows for noise reduction, lower power consumption, and better dynamic range. Each block contains configurable current sources and capacitor banks for maximum adaptability. The blocks were designed, simulated, and fabricated in Cadence using IBM\u27s 130nm CMOS process. The processing blocks were combined into a four by three array and connected using specially designed interconnect fabric. A test structure including the LPF, HPF, and multiplier was also constructed for characterization purposes. The main goals for this project are frequency compression and creating a non-linear energy operator for neural spike detection. The test results for the low-pass filter, integrator, and frequency divider reflected the simulated values. The other blocks didn\u27t perform as well as in simulation. The interconnect fabric ties all the blocks together and achieved maximum configurability with negligible attenuation. In simulation, frequency compression was achieved with 30u[micro]W of power from a 1V supply rail

Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications

Advanced correlation filters have been employed in a wide variety of image processing and pattern recognition applications such as automatic target recognition and biometric recognition. Among those, object recognition and tracking have received more attention recently due to their wide range of applications such as autonomous cars, automated surveillance, human-computer interaction, and vehicle navigation.Although digital signal processing has long been used to realize such computational systems, they consume extensive silicon area and power. In fact, computational tasks that require low to moderate signal-to-noise ratios are more efficiently realized in analog than digital. However, analog signal processing has its own caveats. Mainly, noise and offset accumulation which degrades the accuracy, and lack of a scalable and standard input/output interface capable of managing a large number of analog data.Two digitally-interfaced analog correlation filter systems are proposed. While digital interfacing provided a standard and scalable way of communication with pre- and post-processing blocks without undermining the energy efficiency of the system, the multiply-accumulate operations were performed in analog. Moreover, non-volatile floating-gate memories are utilized as storage for coefficients. The proposed systems incorporate techniques to reduce the effects of analog circuit imperfections.The first system implements a 24x57 Gilbert-multiplier-based correlation filter. The I/O interface is implemented with low-power D/A and A/D converters and a correlated double sampling technique is implemented to reduce offset and lowfrequency noise at the output of analog array. The prototype chip occupies an area of 3.23mm2 and demonstrates a 25.2pJ/MAC energy-efficiency at 11.3 kVec/s and 3.2% RMSE.The second system realizes a 24x41 PWM-based correlation filter. Benefiting from a time-domain approach to multiplication, this system eliminates the need for explicit D/A and A/D converters. Careful utilization of clock and available hardware resources in the digital I/O interface, along with application of power management techniques has significantly reduced the circuit complexity and energy consumption of the system. Additionally, programmable transconductance amplifiers are incorporated at the output of the analog array for offset and gain error calibration. The prototype system occupies an area of 0.98mm2 and is expected to achieve an outstanding energy-efficiency of 3.6pJ/MAC at 319kVec/s with 0.28% RMSE

Low-rank matrix recovery: blind deconvolution and efficient sampling of correlated signals

Low-dimensional signal structures naturally arise in a large set of applications in various fields such as medical imaging, machine learning, signal, and array processing. A ubiquitous low-dimensional structure in signals and images is sparsity, and a new sampling theory; namely, compressive sensing, proves that the sparse signals and images can be reconstructed from incomplete measurements. The signal recovery is achieved using efficient algorithms such as \ell_1-minimization. Recently, the research focus has spun-off to encompass other interesting low-dimensional signal structures such as group-sparsity and low-rank structure. This thesis considers low-rank matrix recovery (LRMR) from various structured-random measurement ensembles. These results are then employed for the in depth investigation of the classical blind-deconvolution problem from a new perspective, and for the development of a framework for the efficient sampling of correlated signals (the signals lying in a subspace). In the first part, we study the blind deconvolution; separation of two unknown signals by observing their convolution. We recast the deconvolution of discrete signals w and x as a rank-1 matrix wx* recovery problem from a structured random measurement ensemble. The convex relaxation of the problem leads to a tractable semidefinite program. We show, using some of the mathematical tools developed recently for LRMR, that if we assume the signals convolved with one another live in known subspaces, then this semidefinite relaxation is provably effective. In the second part, we design various efficient sampling architectures for signals acquired using large arrays. The sampling architectures exploit the correlation in the signals to acquire them at a sub-Nyquist rate. The sampling devices are designed using analog components with clear implementation potential. For each of the sampling scheme, we show that the signal reconstruction can be framed as an LRMR problem from a structured-random measurement ensemble. The signals can be reconstructed using the familiar nuclear-norm minimization. The sampling theorems derived for each of the sampling architecture show that the LRMR framework produces the Shannon-Nyquist performance for the sub-Nyquist acquisition of correlated signals. In the final part, we study low-rank matrix factorizations using randomized linear algebra. This specific method allows us to use a least-squares program for the reconstruction of the unknown low-rank matrix from the samples of its row and column space. Based on the principles of this method, we then design sampling architectures that not only acquire correlated signals efficiently but also require a simple least-squares program for the signal reconstruction. A theoretical analysis of all of the LRMR problems above is presented in this thesis, which provides the sufficient measurements required for the successful reconstruction of the unknown low-rank matrix, and the upper bound on the recovery error in both noiseless and noisy cases. For each of the LRMR problem, we also provide a discussion of a computationally feasible algorithm, which includes a least-squares-based algorithm, and some of the fastest algorithms for solving nuclear-norm minimization.Ph.D