Wireless Testing of Integrated Circuits.

Integrated circuits (ICs) are usually tested during manufacture by means of automatic testing equipment (ATE) employing probe cards and needles that make repeated physical contact with the ICs under test. Such direct-contact probing is very costly and imposes limitations on the use of ATE. For example, the probe needles must be frequently cleaned or replaced, and some emerging technologies such as three-dimensional ICs cannot be probed at all. As an alternative to conventional probe-card testing, wireless testing has been proposed. It mitigates many of the foregoing problems by replacing probe needles and contact points with wireless communication circuits. However, wireless testing also raises new problems which are poorly understood such as: What is the most suitable wireless communication technique to employ, and how well does it work in practice? This dissertation addresses the design and implementation of circuits to support wireless testing of ICs. Various wireless testing methods are investigated and evaluated with respect to their practicality. The research focuses on near-field capacitive communication because of its efficiency over the very short ranges needed during IC manufacture. A new capacitive channel model including chip separation, cross-talk, and misalignment effects is proposed and validated using electro-magnetic simulation studies to provide the intuitions for efficient antenna and circuit design. We propose a compact clock and data recovery architecture to avoid a dedicated clock channel. An analytical model which predicts the DC-level fluctuation due to the capacitive channel is presented. Based on this model, feed-forward clock selection is designed to enhance performance. A method to select proper channel termination is discussed to maximize the channel efficiency for return-to-zero signaling. Two prototype ICs incorporating wireless testing systems were fabricated and tested with the proposed methods of testing digital circuits. Both successfully demonstrated gigahertz communication speeds with a bit-error rate less than 10^−11. A third prototype IC containing analog voltage measurement circuits was implemented to determine the feasibility of wirelessly testing analog circuits. The fabricated prototype achieved satisfactory voltage measurement with 1 mV resolution. Our work demonstrates the validity of the proposed models and the feasibility of near-field capacitive communication for wireless testing of ICs.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/93993/1/duelee_1.pd

Extension of 0.18µm standard CMOS technology operating range to the microwave and millimetre-wave regime

There is an increasing interest in building millimetre-wave circuits on standard digital complementary metal oxide semiconductor (CMOS) technology for applications such as wireless local area networks (WLAN), automotive radar and remote sensing. This stems from the existing low cost, well-developed, high yield infrastructure for mass production. The overall aim of this thesis is to extend the operating range of 0.18um standard logic CMOS technology to millimetre-wave regime. To this end, microwave and millimetre-wave design, optimisation and modelling methodologies for active and passive devices and low noise circuit implementation are described. As part of the evaluation, new systematic and modular ways of making high performance passive and active devices such as spiral inductors, slow-wave coplanar waveguide (CPW) transmission lines, comb capacitors and NMOS transistors are proposed, designed, simulated, fabricated, modelled and analysed. Small-signal and noise de-embedding techniques are developed and verified up to 110 GHz, providing an increased accuracy in the device model, leading to a robust design at millimetre-wave frequencies. Reduced substrate losses resulting in increased quality factor are presented for optimised spiral inductor designs, featuring patterned floating shield (PFS), enabling improved matching network and a reduced chip area. Based on the proposed shielded slow-wave CPW, both the line attenuation and structure length are decreased, resulting in a more compact and simplified circuit design. An optimised transistor design, aimed at reducing the layout parasitic effects, was realised. The optimisation led to a significant improvement in the gain and noise performance of the transistor, extending its operation beyond the cut-off frequency (ft). By combining all the optimised components, low noise amplifiers (LNAs) operating at 25 GHz and 40 GHz were implemented and compared. These LNAs demonstrate state-of-the-art performance, with the 40 GHz LNA exhibiting the highest gain and lowest noise performance of any LNA reported using 0.18um CMOS technology. On the other hand, the 25 GHz LNA showed a comparable performance to other reported results in literature using several topologies implemented in CMOS technology. These findings will provide a framework for expansion to smaller CMOS technology nodes with the view of extending to sub millimetre-wave frequencies

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Development of micromachined millimeter-wave modules for next-generation wireless transceiver front-ends

This thesis discusses the design, fabrication, integration and characterization of millimeter wave passive components using polymer-core-conductor surface micromachining technologies. Several antennas, including a W-band broadband micromachined monopole antenna on a lossy glass substrate, and a Ka-band elevated patch antenna, and a V-band micromachined horn antenna, are presented. All antennas have advantages such as a broad operation band and high efficiency. A low-loss broadband coupler and a high-Q cavity for millimeter-wave applications, using surface micromachining technologies is reported using the same technology. Several low-loss all-pole band-pass filters and transmission-zero filters are developed, respectively. Superior simulation and measurement results show that polymer-core-conductor surface micromachining is a powerful technology for the integration of high-performance cavity, coupler and filters. Integration of high performance millimeter-wave transceiver front-end is also presented for the first time. By elevating a cavity-filter-based duplexer and a horn antenna on top of the substrate and using air as the filler, the dielectric loss can be eliminated. A full-duplex transceiver front-end integrated with amplifiers are designed, fabricated, and comprehensively characterized to demonstrate advantages brought by this surface micromachining technology. It is a low loss and substrate-independent solution for millimeter-wave transceiver integration.Ph.D.Committee Chair: John Papapolymerou; Committee Chair: Manos Tentzeris; Committee Member: Gordon Stuber; Committee Member: John Cressler; Committee Member: John Z. Zhang; Committee Member: Joy Laska

Three-dimensional micromachined on-chip inductors for high frequency applications

Demands for wireless communication are ever-escalating for consumer and military communication applications. The requirements of portability, more functionality and lower cost have been driving forces toward smaller, more sophisticated and flexible wireless devices with lower power consumption. To meet these requirements, monolithically integrated passive inductors with high Q-factors and high self-resonant frequencies are desirable. Q-factor and self-resonant frequency of an inductor are significantly degraded at high frequencies due to conductor ohmic loss, magnetically induced eddy current in the conductive substrate, and lower self-resonant frequency from capacitance between conductive substrate and conductors. In this dissertation, novel three-dimensional arch-like solenoid and dome-shaped spiral inductors are designed, fabricated, and characterized. MEMS-based fabrication techniques such as copper electroplating through voids in thick SU-8 photoresist molds and EAGLE2100 conformal photoresist molds on sacrificial arch-like or dome-shape SJR5740 photoresist mounds are utilized. An air gap between the inductor and the silicon substrate is used to reduce the degradations of inductor performance. According to the Sonnet electromagnetic simulations, 30 μm air-gap suspension over the substrate is an adequate choice for these inductors. Suspended arch-like solenoid copper inductor has flat bottom conductor connected to arch-like top conductor with an air core in between. This design has only 2 contact points per inductor turn to minimize series resistance. Suspended domeshaped spiral copper inductor is fabricated on a sacrificial photoresist dome with the outer end connected to one probe pad, and the inner end connected to the other probe pad through vias and an air-bridge. The sidewalls of spiral turns in this design overlap less with each other thereby reducing inter-turn capacitances. Fabricated inductors are characterized and modeled at high frequencies from Sparameter measurements. ABCD-parameters, derived from the S-parameters are translated into a simplified physical π-model. The resulting arch-like suspended inductors with 2-5 turns have inductances between 0.62 to 0.79 nH, peak Q-factor values between 15.42 to 17 at peak-Q frequencies between 4.7 GHz to 7.0 GHz, and self-resonant frequencies between 47.6 GHz to 88.6 GHz. The 3-turn dome-shaped spiral inductor has inductance of 3.37 nH, peak Q-factor of 35.9 at 1.65 GHz, and self-resonant frequency at 18.74 GHz

Design of Wireless Power Transfer and Data Telemetry System for Biomedical Applications

With the advancement of biomedical instrumentation technologies sensor based remote healthcare monitoring system is gaining more attention day by day. In this system wearable and implantable sensors are placed outside or inside of the human body. Certain sensors are needed to be placed inside the human body to acquire the information on the vital physiological phenomena such as glucose, lactate, pH, oxygen, etc. These implantable sensors have associated circuits for sensor signal processing and data transmission. Powering the circuit is always a crucial design issue. Batteries cannot be used in implantable sensors which can come in contact with the blood resulting in serious health risks. An alternate approach is to supply power wirelessly for tether-less and battery- less operation of the circuits.Inductive power transfer is the most common method of wireless power transfer to the implantable sensors. For good inductive coupling, the inductors should have high inductance and high quality factor. But the physical dimensions of the implanted inductors cannot be large due to a number of biomedical constraints. Therefore, there is a need for small sized and high inductance, high quality factor inductors for implantable sensor applications. In this work, design of a multi-spiral solenoidal printed circuit board (PCB) inductor for biomedical application is presented. The targeted frequency for power transfer is 13.56 MHz which is within the license-free industrial, scientific and medical (ISM) band. A figure of merit based optimization technique has been utilized to optimize the PCB inductors. Similar principal is applied to design on-chip inductor which could be a potential solution for further miniaturization of the implantable system. For layered human tissue the optimum frequency of power transfer is 1 GHz for smaller coil size. For this reason, design and optimization of multi-spiral solenoidal integrated inductors for 1 GHz frequency is proposed. Finally, it is demonstrated that the proposed inductors exhibit a better overall performance in comparison with the conventional inductors for biomedical applications

Reducing signal coupling and crosstalk in monolithic, mixed-signal integrated circuits

Master of ScienceDepartment of Electrical EngineeringWilliam B. KuhnDesigners of mixed-signal systems must understand coupling mechanisms at the system, PC board, package and integrated circuit levels to control crosstalk, and thereby minimize degradation of system performance. This research examines coupling mechanisms in a RF-targeted high-resistivity partially-depleted Silicon-on-Insulator (SOI) IC process and applying similar coupling mitigation strategies from higher levels of design, proposes techniques to reduce coupling between sub-circuits on-chip. A series of test structures was fabricated with the goal of understanding and reducing the electric and magnetic field coupling at frequencies up to C-Band. Electric field coupling through the active-layer and substrate of the SOI wafer is compared for a variety of isolation methods including use of deep-trench surrounds, blocking channel-stopper implant, blocking metal-fill layers and using substrate contact guard-rings. Magnetic coupling is examined for on-chip inductors utilizing counter-winding techniques, using metal shields above noisy circuits, and through the relationship between separation and the coupling coefficient. Finally, coupling between bond pads employing the most effective electric field isolation strategies is examined. Lumped element circuit models are developed to show how different coupling mitigation strategies perform. Major conclusions relative to substrate coupling are 1) substrates with resistivity 1 kΩ·cm or greater act largely as a high-K insulators at sufficiently high frequency, 2) compared to capacitive coupling paths through the substrate, coupling through metal-fill has little effect and 3) the use of substrate contact guard-rings in multi-ground domain designs can result in significant coupling between domains if proper isolation strategies such as the use of deep-trench surrounds are not employed. The electric field coupling, in general, is strongly dependent on the impedance of the active-layer and frequency, with isolation exceeding 80 dB below 100 MHz and relatively high coupling values of 40 dB or more at upper S-band frequencies, depending on the geometries and mitigation strategy used. Magnetic coupling was found to be a strong function of circuit separation and the height of metal shields above the circuits. Finally, bond pads utilizing substrate contact guard-rings resulted in the highest degree of isolation and the lowest pad load capacitance of the methods tested

Characterization and design of CMOS components for microwave and millimeter wave applications

Ph.DDOCTOR OF PHILOSOPH