A 3 GHz spread spectrum clock generator for SATA applications using chaotic PAM modulation

This paper proposes a prototype of a Spread Spectrum Clock Generator which is the first known specifically meant for 3 GHz Serial ATA-II applications. The modulation is obtained from a fractional PLL which employs a Delta-Sigma modulator. A further innovative aspect of our work is that our prototype takes advantage of a chaotic PAM as driving signal, instead a triangular signal as in all spread spectrum generators proposed in literature for SATA-II. In this way we avoid the periodicity of the modulated clock, completely flattening the peaks in the power spectral density. The circuit prototype has been designed n 0.13 μm CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz. The chip active area is 0.27×0.78 mm2 and the power consumption is as low as 14.7 mW. © 2008 IEEE

A spread spectrum clock generator based on a short-term optimized chaotic map

4noWe present a spread spectrum clock generator for EMI reduction, where the modulating signal is generated by a suitably designed chaotic map. With respect to past solutions, the map has been designed to achieve a specific short-term behavior of the generated sequences, which allows to optimize the electromagnetic interference peak reduction not only for the theoretical spectrum, but also in the measurement setting prescibed by CISPR norms. In the latter case, we are able to achieve a 3.8dB improvement in EMI reduction with respect to the triangular modulation when using the peak detector, which increases to 6.9 dB when switching to the quasi-peak detector. Results are measured on a prototype which has been designed and fabricated in a 0.18 μm CMOS technology. © 2011 IEEE.partially_openopenPareschi F.; Setti G.; Rovatti R.; Frattini G.Pareschi, F.; Setti, G.; Rovatti, R.; Frattini, G

A Wide Modulation Range and PVT-Tolerant Spread-Spectrum Modulation Clock Generator

This dissertation presents a phase domain in-loop-bandwidth spread-spectrum clock generation technique. In this proposed technique, a charge-based discrete-time loop filter is proposed to enable the phase domain in-loop-bandwidth spread-spectrum modulation without a delta-sigma modulator or time-to-digital converter. The in-loop-bandwidth modulation technique maximizes the loop bandwidth to improve phase noise suppression in a ring-based voltage-controlled oscillator. The phase domain modulation is established to eliminate a delta-sigma modulator that presents an undesirable power and noise trade-off. An analog-domain phase modulation in this proposed modulation technique eliminates a time-to-digital converter that results in inevitable quantization noise. The proposed technique delivers a wide spread-spectrum modulation range with significantly relaxed PVT sensitivity. Since the proposed discrete time loop filter acquires and filters signals in the charge domain, this loop filter supports good linearity for a wide modulation range. PVT variations in the loop filter and the voltage-controlled oscillator are attenuated by the loop gain. The nonlinearity of the voltage-controlled oscillator gain (K[subscript VCO]) and loop filter is also attenuated due to the loop gain. In addition, a correlated double sampling technique is leveraged to minimize 1/f noise and DC offset of the proposed discrete-time loop filter. This dissertation discusses design trade-offs: between reference frequency and spread-spectrum modulation range, and between the spread-spectrum modulation range and jitter performance. From time and spectral measurements for various reference frequencies, a higher reference frequency results in better jitter performances, but also a narrow spread-spectrum modulation range. Time domain jitter measurements are compared to spectral domain jitter calculations to observe design intuitions. This wide modulation range and PVT-tolerant spread-spectrum modulation technique is implemented in a 0.18µm CMOS, while consuming 9.93mW with a 1.8V power supply. The proposed charge-based discrete time loop filter consumes less than 10% of the total power, and the spread-spectrum modulation component requires less than 5% of the total power. This wide range spread-spectrum clock generation technique achieves 0.8% and 3.2% spread-spectrum modulation range with 22.76dB and 26.51dB spread-spectrum attenuation for 2MHz and 8MHz reference frequencies, respectively. The measured absolute jitter is 62.72ps[subscript rms] and 18.72ps[subscript rms] for 2MHz and 8MHz reference frequencies, respectively. The measured period jitter is 961.2fs[subscript rms] and 988.1fs[subscript rms] for 2MHz and 8MHz reference frequencies, respectively. Finally, a 142% change in KVCO results in less than 298ppm modulation range error, which confirms the PVT-tolerant modulation

A 3 GHz Spread Spectrum Clock Generator for SATA applications using chaotic PAM modulation

This paper proposes a prototype of a Spread Spectrum Clock Generator which is the first known specifically meant for 3 GHz Serial ATA-II applications. The modulation is obtained from a fractional PLL which employs a Delta-Sigma modulator. A further innovative aspect of our work is that our prototype takes advantage of a chaotic PAM as driving signal, instead a triangular signal as in all spread spectrum generators proposed in literature for SATA-II. In this way we avoid the periodicity of the modulated clock, completely flattening the peaks in the power spectral density. The circuit prototype has been designed in 0.13 μm CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz. The chip active area is 0.27 70.78 mm2 and the power consumption is as low as 14.7 mW

A 3 GHz spread spectrum clock generator for SATA applications using chaotic PAM modulation

This paper proposes a prototype of a Spread Spectrum Clock Generator which is the first known specifically meant for 3 GHz Serial ATA-II applications. The modulation is obtained from a fractional PLL which employs a Delta-Sigma modulator. A further innovative aspect of our work is that our prototype takes advantage of a chaotic PAM as driving signal, instead a triangular signal as in all spread spectrum generators proposed in literature for SATA-II. In this way we avoid the periodicity of the modulated clock, completely flattening the peaks in the power spectral density. The circuit prototype has been designed n 0.13 μm CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz. The chip active area is 0.27×0.78 mm2 and the power consumption is as low as 14.7 mW

XXV Congreso Argentino de Ciencias de la Computación - CACIC 2019: libro de actas

Trabajos presentados en el XXV Congreso Argentino de Ciencias de la Computación (CACIC), celebrado en la ciudad de Río Cuarto los días 14 al 18 de octubre de 2019 organizado por la Red de Universidades con Carreras en Informática (RedUNCI) y Facultad de Ciencias Exactas, Físico-Químicas y Naturales - Universidad Nacional de Río CuartoRed de Universidades con Carreras en Informátic

XXV Congreso Argentino de Ciencias de la Computación - CACIC 2019: libro de actas

Trabajos presentados en el XXV Congreso Argentino de Ciencias de la Computación (CACIC), celebrado en la ciudad de Río Cuarto los días 14 al 18 de octubre de 2019 organizado por la Red de Universidades con Carreras en Informática (RedUNCI) y Facultad de Ciencias Exactas, Físico-Químicas y Naturales - Universidad Nacional de Río CuartoRed de Universidades con Carreras en Informátic