Carbonyl-Iron/Epoxy Composite Magnetic Core for Planar Power Inductor Used in Package-Level Power Grid

Our research objective is to realize the basic technology for a next generation package-level power grid (PLPG) for plural application large scale integrated circuits (LSIs). In this study, a carbonyl-iron powder (CIP)/epoxy composite magnetic core, for large-current power inductor used for the main dc-dc converter in the PLPG, has been fabricated and evaluated. 54 vol.%-CIP/epoxy composite core made by screen-printing had a relative permeability of 7.5 and loss tangent of about 0.03 at 100 MHz. The planar power inductor using composite core was fabricated and evaluated, which had a quasi closed magnetic circuit consisting of low permeability composite core and embedded 35-mu m-thick, two-turn copper spiral coil. The fabricated inductor with a 1-mm-square in size had 5.5 nH inductance, Q-factor of 15 at 100 MHz, and 18 m Omega dc coil resistance. Inductance was constant even when the superimposed dc current increased up to around 5.5 A.ArticleIEEE TRANSACTIONS ON MAGNETICS. 49(7):4172-4175 (2013)journal articl

Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis

Modern Systems-on-Chip (SoC) architectures and CPU+FPGA computing platforms are moving towards heterogeneous systems featuring an increasing number of hardware accelerators. These specialized components can deliver energy-efficient high performance, but their design from high-level specifications is usually very complex. Therefore, it is crucial to understand how to design and optimize such components to implement the desired functionality. This paper discusses the challenges between software programmers and hardware designers, focusing on the state-of-the-art methods based on high-level synthesis (HLS). It also highlights the future research lines for simplifying the creation of complex accelerator-based architectures

Integrated Voltage Regulators with Thin-Film Magnetic Power Inductors

Integration of alternative materials and devices with CMOS will expand functionality and improve performance of established applications in the era of diminishing returns from Moore's Law scaling. In particular, integration of thin-film magnetic materials will enable improvements in energy efficiency of digital computing applications by enabling integrated power conversion and management with on-chip power inductors. Integrated voltage reg- ulators will also enable fine-grained power management, by providing dynamic scaling of the supply voltage in concert with the clock frequency of synchronous logic to throttle power consumption at periods of low computational demand. Implementation of integrated power conversion requires high capacity energy storage devices. This is best achieved with integration of thin-film magnetic materials for high quality on-chip power inductors. This thesis describes a body of work conducted to develop integrated switch-mode voltage regulators with thin-film magnetic power inductors. Soft-magnetic materials and inductor topologies are selected and optimized, with intent to maximize efficiency and current density of the integrated regulators. Custom integrated circuits are designed and fabricated in 45nm-SOI to provide the control system and power-train necessary to drive the power inductors. A silicon interposer is designed and fabricated in collaboration with IBM Research to integrate custom power inductors by 2.5D chip stacking, enabling power conversion with current density greater than 10A/mm2. The concepts and designs developed from this work will enable significant improvements in performance-per-watt of future microprocessors

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

Emerging technologies provide SoCs with fine-grained DVFS capabilities both in space (number of domains) and time (transients in the order of tens of nanoseconds). Analyzing these systems requires cycle-accurate accounting of rapidly-changing dynamics and complex interactions among accelerators, interconnect, memory, and OS. We present an FPGA-based infrastructure that facilitates such analyses for high-performance embedded systems. We show how our infrastructure can be used to first generate SoCs with loosely-coupled accelerators, and then perform design-space exploration considering several DVFS policies under full-system workload scenarios, sweeping spatial and temporal domain granularity

PowerCool: Simulation of Integrated Microfluidic Power Generation in Bright Silicon MPSoCs

Integrated microfluidic power generation and power delivery promises to be a disruptive packaging technology with the potential to combat dark silicon. It essentially consists of integrated microchannel-based electrochemical “flow cells” in a 2D/3D multiprocessor system-on-chip (MPSoC), that generate electricity to power up the entire or part of the chip, while also simultaneously acting as a high-efficiency microfluidic heat sink. Further development of this technology requires efficient modeling tools that would assess the efficacy of such solutions and help perform early-stage design space exploration. In this paper, we propose a compact mathematical model, called Power- Cool, that performs electro-chemical modeling and simulation of integrated microfluidic power generation in MPSoCs. The accuracy of the model has been validated against fine-grained multiphysics simulations of flow cells in the COMSOL software that is unsuitable for EDA because of large simulation times. PowerCool model is demonstrated to be up to 425x times faster than COMSOL simulations while incurring a worst-case error of only 5%. Furthermore, the PowerCool model has been used to study and assess the efficacy of this technology for a test MPSoC

An Overview of Fully Integrated Switching Power Converters Based on Switched-Capacitor versus Inductive Approach and Their Advanced Control Aspects

This paper reviews and discusses the state of the art of integrated switched-capacitor and integrated inductive power converters and provides a perspective on progress towards the realization of efficient and fully integrated DC–DC power conversion. A comparative assessment has been presented to review the salient features in the utilization of transistor technology between the switched-capacitor and switched inductor converter-based approaches. First, applications that drive the need for integrated switching power converters are introduced, and further implementation issues to be addressed also are discussed. Second, different control and modulation strategies applied to integrated switched-capacitor (voltage conversion ratio control, duty cycle control, switching frequency modulation, Ron modulation, and series low drop out) and inductive converters (pulse width modulation and pulse frequency modulation) are then discussed. Finally, a complete set of integrated power converters are related in terms of their conditions and operation metrics, thereby allowing a categorization to provide the suitability of converter technologies

High-current integrated battery chargers for mobile applications

Battery charging circuits for mobile applications, such as smart phones and tablets, require both small area and low losses. In addition, to reduce the charging time, high current is needed through the converter. In this work, exploration of the Buck, the 3-Level Buck and the Hybrid Buck converter is performed over the input voltage, the total FET area and the load current. An analytical loss model for each topology is constructed and constrated by experimental results. In addition, packaging and bond wire impact on on-chip losses is analyzed by 3D modeling. Finally, a comparison between the topologies is presented determining potential candidates for a maximum on-chip loss of 2 W at output voltage of 4 V and 10 A of output current