On-chip jitter measurement for true random number generators

Applications of true random number generators (TRNGs) span from art to numerical computing and system security. In cryptographic applications, TRNGs are used for generating new keys, nonces and masks. For this reason, a TRNG is an essential building block and often a point of failure for embedded security systems. One type of primitives that are widely used as source of randomness are ring oscillators. For a ring-oscillator-based TRNG, the true randomness originates from its timing jitter. Therefore, determining the jitter strength is essential to estimate the quality of a TRNG. In this paper, we propose a method to measure the jitter strength of a ring oscillator implemented on an FPGA. The fast tapped delay chain is utilized to perform the on-chip measurement with a high resolution. The proposed method is implemented on both a Xilinx FPGA and an Intel FPGA. Fast carry logic components on different FPGAs are used to implement the fast delay line. This carry logic component is designed to be fast and has dedicated routing, which enables a precise measurement. The differential structure of the delay chain is used to thwart the influence of undesirable noise from the measurement. The proposed methodology can be applied to other FPGA families and ASIC designs

Improved FPGA time-to-digital converter architecture to improve precision, converter linearity and reduce dead-time

Time-to-digital converters (TDCs) and time correlated single photon counters (TCSPC) are instruments commonly used in LiDAR systems, quantum optics experiments and many other applications. This work presents a new time-to-digital converter architecture to improve dead time, converter linearity and precision. The priority encoder is a large combinatorial logic circuit and is often the bottleneck in field programmable gate array (FPGA) TDC designs, as the conversion must complete within the TDC's clock period. This work utilizes a new dual clock domain architecture which has allowed for the TDC clock rate to increase by 38.1% from previous work and potentially double for more modern FPGA devices. This reduces the required delay line length and allows for more precise and linear converters as both integral non-linearity and measurement uncertainty scale according to the square root of the number of delay elements used in the delay line. Single shot precision has improved by 12.9% and converter differential non-linearity and integral non-linearity has reduced by 1.27 and 1.57 least significant bits respectively. This work demonstrates a significant improvement to the performance of FPGA based TDCs at the expense of using slightly more block random access memory

Pentimento: Data Remanence in Cloud FPGAs

Cloud FPGAs strike an alluring balance between computational efficiency, energy efficiency, and cost. It is the flexibility of the FPGA architecture that enables these benefits, but that very same flexibility that exposes new security vulnerabilities. We show that a remote attacker can recover "FPGA pentimenti" - long-removed secret data belonging to a prior user of a cloud FPGA. The sensitive data constituting an FPGA pentimento is an analog imprint from bias temperature instability (BTI) effects on the underlying transistors. We demonstrate how this slight degradation can be measured using a time-to-digital (TDC) converter when an adversary programs one into the target cloud FPGA. This technique allows an attacker to ascertain previously safe information on cloud FPGAs, even after it is no longer explicitly present. Notably, it can allow an attacker who knows a non-secret "skeleton" (the physical structure, but not the contents) of the victim's design to (1) extract proprietary details from an encrypted FPGA design image available on the AWS marketplace and (2) recover data loaded at runtime by a previous user of a cloud FPGA using a known design. Our experiments show that BTI degradation (burn-in) and recovery are measurable and constitute a security threat to commercial cloud FPGAs.Comment: 17 Pages, 8 Figure

Utilisation de la reconfiguration dynamique des FPGA pour le contrôle précis et exact des délais dans les convertisseurs temps à numérique

RÉSUMÉ La mesure d'intervalles de temps est importante dans différents domaines d'applications scientifiques. Un convertisseur numérique de temps (TDC) est un circuit électronique permettant de mesurer des intervalles de temps avec des résolutions de l'ordre de la picoseconde. Jusqu'à la dernière décennie, ces circuits étaient implémentés exclusivement sous forme de circuits dédiés (ASIC), mais depuis, plusieurs implémentations sur circuits programmables (FPGA) ont été proposées. Bien qu'à ce jour de telles implémentations accusent toujours des performances inférieures, il existe un intérêt réel pour réduire l'importance de cet écart. En effet, le progrès fulgurant de la technologie FPGA, en termes de densité logique et de fréquence d'opération, en fait aujourd'hui un candidat de choix pour l'implémentation de nombreux circuits et systèmes. Au delà du grand degré d'intégration qu'elle permet d'obtenir, ce type d'implémentation se démarque des circuits dédiés en ce qu'elle permet à la fois des temps de développement et des coûts non-récurrents nettement moins importants. C'est donc dans ce contexte que ce travail se penche sur l'implémentation FPGA d'un convertisseur numérique de temps. Alors que les implémentations de TDC sur circuits dédiés permettent d'obtenir des résolutions avoisinant la picoseconde, les implémentations FPGA les plus récentes sont limitées à quelques dizaines de picosecondes. Puisque l'implémentation d'un TDC est intimement liée à la notion de délai, les FPGAs sont handicapés d'une part par l'irrégularité des délais d'interconnexions programmables générées par les outils de synthèse, et d'autre part par des délais d'interconnexions plus importants. C'est ainsi que les implémentations FPGA offrant les meilleures performances dans la littérature reposent sur une architecture permettant d'exploiter la présence des structures d'interconnexions dédiés, telle la chaine de retenue rapide. En effet, ces structures d'interconnexions dédiées offrent à la fois des délais réduits et une régularité accrue. Toutefois, la résolution atteignable avec cette architecture est limitée par les délais minimaux du circuit, et ces derniers sont sensiblement plus importants sur un FPGA que sur un circuit dédié. Néanmoins, cette architecture bénéficie directement des nouvelles générations de FPGA qui sont produites avec des procédés de fabrication permettant d'obtenir des délais minimaux réduits.-----------------ABSTRACT Time interval measurement is important in various scientific and engineering applications. A Time-to-Digital Converter (TDC) is an integrated circuit allowing measurement of time intervals with resolutions and precisions down to a picosecond. Until the last decade or so, these circuits were implemented exclusively as application specific integrated circuits (ASIC), but since then, various implementations targeting field-programmable gate arrays (FPGA) have been proposed. While these implementations still deliver reduced performances in terms of resolution and precision, there is a growing interest within the scientific community to reduce this gap. Indeed, with the dazzling progress of the FPGA technology over the past decade, both in terms of logic density and operation frequency, it is becoming a implementation target of choice for an ever growing range of circuit and systems. Two key benefits from such implementations are considerably reduced development times and non-recurring costs. It is therefore in this context that this work is focused on the FPGA implementation of time-to-digital converters. While ASIC implementations of TDC can enable resolutions neighbouring a single picosecond, most recent FPGA implementations are still limited to a few tens of picoseconds. As the implementation of a TDC is closely related to the notion of delay, FPGAs are handicapped both by the irregularity of interconnection delays, and increased minimal delays. Therefore, to this day, the most successful FPGA implementations that have been proposed in the literature rely on architectures allowing to take advantage of dedicated interconnection structures, such as the carry-chain used in arithmetic circuits. Indeed, these dedicated interconnection structures provide both reduced delays and increased interconnection delay regularity. However, the resolution achievable with such architecture is limited by the minimal delays available on the circuit, which are substantially more important on an FPGA than on an ASIC. Nevertheless, this architecture directly benefits from newer generations of FPGAs, produced with fabrication processes that enable reduced minimal delay