A Sub-10ps Time-to-Digital Converter with 204ns Dynamic Range For Time-resolved Imaging and Ranging Applications

Time-resolved quantization has become inherent in systems that incorporate a Time-of-Flight (ToF) or Time-of-Arrival (ToA) measurement. Such systems have diverse applications ranging from direct time-of-flight measurements in 3D ranging systems such as Radar and Lidar systems to imaging systems using Time-Correlated Single Photon Counting (TCSPC) (in fields such as nuclear instrumentation, molecular biology, artificial vision in computer systems, etc.). Time resolution in the order of picoseconds, especially in imaging applications has become important due to the increasing demands on the functionality and accuracy of the DSP (digital signal processing) in such systems. The increasing density of integration in CMOS implementations of such imaging and ranging systems places large constrains on area and power consumption. Furthermore, the increased variability of the range of the measurement quantities introduces an undesirable trade-off between dynamic range and precision/resolution. Therefore there is a need for time-to-digital converters which achieve high precision, high resolution and large dynamic range, without excessive costs in area and power. In this thesis, a wide range, high resolution TDC is designed to offer a timing resolution of less than 10ps and a dynamic range of 204.8ns. This is achieved by using a digitally-intensive hierarchical approach, using two looped structures, which incorporates a novel control logic algorithm. This guarantees accurate operation of the loops, removing the possibility of MSB errors in the digital word. Firstly the measurement is subdivided into 2 different sections: a coarse quantization and a fine quantization. Both of the conversion steps involve the use of a looped delay–line structure utilizing only 4 elements per delay line. This together with the control logic, makes the design of a wide dynamic range TDC achievable without excessive area and power consumption. The design has been simulated, fabricated and tested in the IBM 0.18μm technology. The proposed design achieves a resolution of 8.125ps with an input dynamic range of 204.8ns, a maximum input occurrence rate of 100MHz and a minimum dead time of 7.5ns. The fabricated TDC has a power consumption of < 20mW (1.8V supply; FSR signal at 4MS/s) and < 35mW at the maximum output rate of 100MS/s