Efficient simulation of solution curves and bifurcation loci in injection-locked oscillators

A new method is presented for the two-level harmonic-balance analysis of multivalued synchronized solution curves in injection-locked oscillators. The method is based on the extraction of a nonlinear admittance function, which describes the circuit response from the input source terminals. It does not require any optimization or parameter switching procedures, this constituting a significant advantage compared with previous analysis techniques. With additional mathematical conditions, it enables a straightforward determination of the turning point and Hopf bifurcation loci that delimit the stable injection-locked operation bands. The codimension two bifurcation point at which the turning point and Hopf bifurcation loci merge is analyzed in detail, as well as the saddle-connection locus. As it is shown, a second intersection of the saddle-connection locus with the turning point locus acts as a boundary between synchronization points and points associated with jumps and hysteresis. The likely observation of chaotic solutions in the neighborhood of the saddle-connection locus is discussed too. The techniques have been validated by application to several injection-locked oscillators, obtaining good agreement with the experimental results.This work was supported by the Spanish Ministry of Economy and competitiveness under contract TEC2011-29264-C03-01 and the predoctoral fellowship for researchers in training of the University of Cantabria and the Regional Ministry of Education of the Government of Cantabria

A 1.8-GHz Injection-Locked Quadrature CMOS VCO With Low Phase Noise and High Phase Accuracy

Injection-locked quadrature voltage-controlled oscillators are introduced in this paper as high accuracy, low phase noise, and low-power I and Q generators. A master voltage-controlled osciflator (VCO), running at twice the output frequency, locks two coupled VCOs. The former determines phase noise while the latter sets phase accuracy, thus, breaking the tradeoff between the two parameters, the main limit of free running coupled VCOs, recently proposed in the framework of highly integrated solutions. The proposed design has been tailored to DCS 1800 and prototypes have been fabricated in a 0.18-mu m CMOS technology. Experiments show a phase noise of -127 dBc/Hz and -139 dBc/Hz at 600 kHz and 3 MHz, respectively, while consuming 10 mA from 1.8 V supply. A 185-dB state-of-the-art phase noise figure of merit results. Accuracy between output signals is determined by means of image band rejection (HIR) measurements on a purposely developed single-side-band upconversion mixer. Minimum IBR among 20 samples is as large as 46 dB