Investigating thermal dependence on monolithically-integrated photonic interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 59-61).Monolithically-integrated optical link is a disruptive technology which has the promising potential to remove memory bandwidth bottleneck in the deep multicore regime. Although with the advantages of high bandwidth-density and energy-efficiency, it comes with design challenges from device, architecture and system perspectives. High thermal sensitivity of the essential optical ring resonator imposes constraints on the applicability of optical links in the electro-optical systems. To investigate the thermal dynamics as well as to develop advanced ring thermal-tuning mechanisms, real-time thermal monitoring at design stage is required. In this work we propose a thermal simulation platform which integrates system modeling aspects including the high-level architectural performance model, the physical device evaluation model, and the thermal analysis model. By introducing the compact thermal model with linear transient thermal analysis solver, system thermal dynamics can be monitored at high efficiency. We demonstrate the temperature profile of a multi-core microprocessor system running real workloads. The evaluation results show the system thermal dependence on the manufacturing process, circuit thermal crosstalk and integrated ring heater efficiency.by Yu-Hsin Chen.S.M

Design of Optical Interconnect Transceiver Circuits and Network-on-chip Architectures for Inter- and Intra-chip Communication

The rapid expansion in data communication due to the increased multimedia applications and cloud computing services necessitates improvements in optical transceiver circuitry power efficiency as these systems scale well past 10 Gb/s. In order to meet these requirements, a 26 GHz transimpedance amplifier (TIA) is presented in a 0.25-µm SiGe BiCMOS technology. It employs a transformer-based regulated cascode (RGC) input stage which provides passive negative-feedback gain that enhances the effective transconductance of the TIA’s input common-base transistor; reducing the input resistance and pro- viding considerable bandwidth extension without significant noise degradation or power consumption. The TIA achieves a 53 dBΩ single-ended transimpedance gain with a 26√ GHz bandwidth and 21.3 pA/H z average input-referred noise current spectral density. Total chip power including output buffering is 28.2 mW from a 2.5 V supply, with the core TIA consuming 8.2 mW, and the chip area including pads is 960 µm × 780 µm. With the advance of photonic devices, optical interconnects becomes a promising technology to replace the conventional electrical channels for the high-bandwidth and power efficient inter/intra-chip interconnect. Second, a silicon photonic transceiver is presented for a silicon ring resonator-based optical interconnect architecture in a 1V standard 65nm CMOS technology. The transmitter circuits incorporate high-swing drivers with non-linear pre-emphasis and automatic bias-based tuning for resonance wavelength stabilization. An optical forwarded-clock adaptive inverter-based transimpedance amplifier (TIA) receiver trades-off power for varying link budgets by employing an on-die eye monitor and scaling the TIA supply for the required sensitivity. At 5 GB/s operation, the ring modulator un- der 4Vpp driver achieves 12.7dB extinction ratio with 4.04mW power consumption, while a 0.28nm tuning range is obtained at 6.8µW/GHz efficiency with the bias-based tuning scheme implemented with the 2Vpp transmitter. When tested with a wire-bonded 150f- F p-i-n photodetector, the receiver achieves -12.7dBm sensitivity at a BER=10−15 and consumes 2.2mW at 8 GB/s. Third, a novel Nano-Photonic Network-on-Chip (NoC) architecture, called LumiNoC, is proposed for high performance and power-efficient interconnects for the chip-multi- processors (CMPs). A 64-node LumiNoC under synthetic traffic enjoys 50% less latency at low loads versus other reported photonic NoCs, and ∼25% less latency versus the electrical 2D mesh NoCs on realistic workloads. Under the same ideal throughput, LumiNoC achieves laser power reduction of 78%, and overall power reduction of 44% versus competing designs

Modeling of Photonic Devices and Photonic Integrated Circuits for Optical Interconnect and RF Photonic Front-End Applications

Photonic integrated circuits (PICs) offer compelling solutions for applications in many areas due to the sufficient functionality and excellent performance. Optical interconnects and radio frequency (RF) photonics are two areas in which PICs have potential to be widely used. Optical interconnect system efficiency is dependent on the ability to optimize the transceiver circuitry for low-power and high-bandwidth operation, motivating co-simulation environments with compact optical device simulation models. Compact models for vertical-cavity surface-emitting lasers (VCSELs) and silicon carrier-injection/depletion ring modulators which include both non-linear electrical and optical dynamics are presented, and excellent matching between co-simulated and measured optical eye diagrams is achieved. Advanced modulation schemes, such as four-level pulse-amplitude modulation (PAM4), are currently under consideration in both high-speed electrical and optical interconnect systems. How NRZ and PAM4 modulation impacts the energy efficiency of an optical link architecture based on silicon photonic microring resonator modulators and drop filters is analyzed. Two ring modulator device structures are proposed for PAM4 modulation, including a single-segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Modeling results show that the PAM4 architectures achieve superior energy efficiency at higher data rates due to the relaxed circuit bandwidth. While RF photonics offer the promise of chip-scale opto-electrical systems with high levels of functionality, in order to avoid long and unsuccessful design cycles, efficient models that allow for co-simulation are necessary. In order to address this, an optical element modeling framework is proposed based on Verilog-A which allows for the co-simulation of optical elements with transistor-level circuits in a Cadence design environment. Three components in the RF photonic system, Mach Zehnder (MZ) modulators, 4th order all pass filter (APF)-based optical filters, and jammer-suppression notch filters are presented to demonstrate the capability of efficient system design in co-simulation environments

Large-Scale Photonics Integration: Data Communications to Optical Beamforming

Integrated photonics is an emerging technology that has begun to transform our way of life with the same amount of impact that integrated CMOS electronics has. Currently, photonics integration is orders of magnitude less complicated than its electronics counterparts. Nonetheless, it serves as one of the main driving forces to meet the exponentially increasing demand for high-speed and low-cost data transfer in the Information Age. It also promises to provide solutions for next-generation high-sensitivity image sensors and precision metrology and spectroscopy instruments. In this thesis, integrated photonics architectures for solid-state photonic beamforming and processing are investigated for high-resolution and high sensitivity lens-free transceiver applications. Furthermore, high-efficiency integrated electro-optical modulators aiming to meet the demand of high-density photonic integration with improved modulation efficiency, small footprint, and lower insertion loss are investigated. Two integrated photonic solid-state beamforming architectures incorporating two-dimensional apertures are explored. First, a novel transceiver architecture for remote sensing, coherent imaging, and ranging applications is demonstrated. It reduces system implementation complexity and offers a methodology for very-large-scale coherent transceiver beamforming applications. Next, a transmitter beamforming architecture inspired by the diffraction pattern of the slit annular ring is analyzed and demonstrated. This transceiver architecture can be used for coherent beamforming applications such as imaging and point-to-point optical communication. Finally, a coherent imager architecture for high-sensitivity three-dimensional imaging and remote-sensing applications is present. This novel architecture can suppress undesired phase fluctuations of the optical carrier signal in the illumination and reference paths, providing higher resolution and higher acquisition speed than previous implementations. Moreover, several compact, high-speed CMOS compatible modulators that enable high-density photonic integration are explored. Ultra-compact and low insertion loss silicon-organic-hybrid modulators are designed and implemented for high-speed beamforming and high-efficiency complex signal modulation applications. Finally, a novel integrated nested-ring assisted modulator topology is analyzed and implemented for high-density and high modulation efficiency applications.</p

Resource and thermal management in 3D-stacked multi-/many-core systems

Continuous semiconductor technology scaling and the rapid increase in computational needs have stimulated the emergence of multi-/many-core processors. While up to hundreds of cores can be placed on a single chip, the performance capacity of the cores cannot be fully exploited due to high latencies of interconnects and memory, high power consumption, and low manufacturing yield in traditional (2D) chips. 3D stacking is an emerging technology that aims to overcome these limitations of 2D designs by stacking processor dies over each other and using through-silicon-vias (TSVs) for on-chip communication, and thus, provides a large amount of on-chip resources and shortens communication latency. These benefits, however, are limited by challenges in high power densities and temperatures. 3D stacking also enables integrating heterogeneous technologies into a single chip. One example of heterogeneous integration is building many-core systems with silicon-photonic network-on-chip (PNoC), which reduces on-chip communication latency significantly and provides higher bandwidth compared to electrical links. However, silicon-photonic links are vulnerable to on-chip thermal and process variations. These variations can be countered by actively tuning the temperatures of optical devices through micro-heaters, but at the cost of substantial power overhead. This thesis claims that unearthing the energy efficiency potential of 3D-stacked systems requires intelligent and application-aware resource management. Specifically, the thesis improves energy efficiency of 3D-stacked systems via three major components of computing systems: cache, memory, and on-chip communication. We analyze characteristics of workloads in computation, memory usage, and communication, and present techniques that leverage these characteristics for energy-efficient computing. This thesis introduces 3D cache resource pooling, a cache design that allows for flexible heterogeneity in cache configuration across a 3D-stacked system and improves cache utilization and system energy efficiency. We also demonstrate the impact of resource pooling on a real prototype 3D system with scratchpad memory. At the main memory level, we claim that utilizing heterogeneous memory modules and memory object level management significantly helps with energy efficiency. This thesis proposes a memory management scheme at a finer granularity: memory object level, and a page allocation policy to leverage the heterogeneity of available memory modules and cater to the diverse memory requirements of workloads. On the on-chip communication side, we introduce an approach to limit the power overhead of PNoC in (3D) many-core systems through cross-layer thermal management. Our proposed thermally-aware workload allocation policies coupled with an adaptive thermal tuning policy minimize the required thermal tuning power for PNoC, and in this way, help broader integration of PNoC. The thesis also introduces techniques in placement and floorplanning of optical devices to reduce optical loss and, thus, laser source power consumption.2018-03-09T00:00:00