Joint Phase-Time Arrays: A Paradigm for Frequency-Dependent Analog Beamforming in 6G

Hybrid beamforming is an attractive solution to build cost-effective and energy-efficient transceivers for millimeter-wave and terahertz systems. However, conventional hybrid beamforming techniques rely on analog components that generate a frequency flat response such as phase-shifters and switches, which limits the flexibility of the achievable beam patterns. As a novel alternative, this paper proposes a new class of hybrid beamforming called Joint phase-time arrays (JPTA), that additionally use true-time delay elements in the analog beamforming to create frequency-dependent analog beams. Using as an example two important frequency-dependent beam behaviors, the numerous benefits of such flexibility are exemplified. Subsequently, the JPTA beamformer design problem to generate any desired beam behavior is formulated and near-optimal algorithms to the problem are proposed. Simulations show that the proposed algorithms can outperform heuristics solutions for JPTA beamformer update. Furthermore, it is shown that JPTA can achieve the two exemplified beam behaviors with one radio-frequency chain, while conventional hybrid beamforming requires the radio-frequency chains to scale with the number of antennas to achieve similar performance. Finally, a wide range of problems to further tap into the potential of JPTA are also listed as future directions.Comment: The paper is a revised version of the IEEE Access paper, that includes the full operation of Algorithms 1-3 to help curtail incorrect implementation

Programmable Active Mirror: A Scalable Decentralized Router

This work proposes and demonstrates the scalable router array that eliminates the internal centralization of conventional arrays, unlocking scalability, and the potential for a system composed of spatially separated elements that do not share a common timing reference. Architectural variations are presented, and their specific tradeoffs are discussed. The general operation, steering capabilities, signal and noise considerations, and timing control advantages are evaluated through analysis, simulation, and measurements. An element-level CMOS radio frequency integrated circuit (RFIC) is developed and used to demonstrate a four-element 25 GHz prototype router. The RFIC's programmable true time delay (TTD) control is used to correct path-length-difference-induced intersymbol interference (ISI) and improve a rerouted 270-Mb/s 64-QAM constellation from a completely scrambled state to an EVM of 4% rms (-28 dB). The prototype scalable router's concurrent dual-beam capabilities are demonstrated by simultaneously steering two full power beams at 24.9 and 25 GHz in two different directions in a free-space electromagnetic setup

Receive mode time modulated antenna array incorporating subsampling -theoretical concept and laboratory investigation

An eight element Subsampling Time Modulated Array (STMA) operating in receive mode with a carrier at 2.4 GHz is presented and demonstrated using bespoke Radio Frequency (RF) hardware. Each STMA cell incorporates subsampling functionality, with the sampling frequency significantly below the carrier frequency and requiring minimal additional hardware. By using this concept, the hardware required for a receiver incorporating an antenna array can be reduced and costs saved. STMA design equations and architecture strategies are presented, and a prototype hardware demonstrator is introduced. Laboratory measurements confirm that a received radiated signal, arranged to use the fundamental or a harmonic beam pointed at the radiating source, can be resolved from the subsampled intermediate frequency (IF) output. The concept demonstration hardware provides a measured array conversion gain of 11.4 dBi on the boresight beam, 7.8 dBi on the first positive and 11.3 dBi on the first negative harmonic beams, as resolved at the final combined IF output. The array IF output Signal to Noise and Distortion ratio is 69 dB. The dependence of array sidelobe level performance on STMA sampling switch rise time is also uncovered, though good performance with real, imperfect, hardware is still obtained

Low-Noise Amplifier and Noise/Distortion Shaping Beamformer

The emergence of advanced technologies has increased the need for fast and efficient mobile communication that can facilitate transferring large amounts of data and simultaneously serve multiple users. Future wireless systems will rely on millimeter-wave frequencies, enabled by recent silicon hardware advancements. High-frequency millimeter-wave technology and low-noise receiver front ends and amplifiers are key for improved performance and energy efficiency. This thesis proposes two LNA topologies that offer wide input-power-matched bandwidths and low noise figures, eliminating the need for complex matching networks at the LNA input. These topologies use intrinsic feedback through gate-drain networks and/or the resistance of the SOI-transistor back-gate terminal to achieve the real part of the input impedance. The two LNAs are experimentally demonstrated with two 22-nm FDSOI LNAs. One LNA, matched with the assistance of the gate-drain network, exhibits a bandwidth ranging from 7.7-33.3 GHz, which is further improved to 6-38.7 GHz through the application of the back-gate-resistance method. The two LNAs have noise-figure minima of 1.8 and 1.9 dB, maximum gains of 14.7 and 15.6 dB, and maximum IP1dBs of -9.1 and -7.8 dBm while consuming 10 and 7.8 mW of power and occupying 0.04 and 0.03 mm^2 of active areas, respectively. This thesis also presents the first experimental demonstration of noise/distortion (ND) shaping beamformer. The NDs originating in the receiver itself are spatio-temporally shaped away from the beamformer region of support, thereby permitting their suppression by the beamformer. The demonstrator is a 24.3-28.7 GHz, 79.28 mW 4-port receiver for a 4-element antenna array implemented in 22-nm FDSOI CMOS. When shaping was enabled, the concept demonstrator provided average improvements to the NF and IP1dB of 1.6 dB and 2.25 dB, respectively (compared to a reference design), and achieved NF=2.6 dB and IP1dB=-18.7dBm while consuming 19.8 mW/channel

Digital Beamforming Applications and Demonstrations of an RF System-on-a-Chip

EM phased array system bandwidth is conventionally constrained by the use of phase shifters for beamsteering, which results in beam squint and pulse dispersion of wideband signals. Wideband antenna performance can be achieved through the use of element-level true time delay (TTD) units, but this is often impractical due to the complexities associated with TTD analog devices. The continued improvement of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC) places digital signal conversion at the element level. This allows TTD beamsteering to be accomplished digitally via a combination of integer-sample delays and fractional-sample delay finite impulse response (FIR) filters, enabling support for wideband communication and radar imaging operating modes. As phased array systems rely on matched channel characteristics, accurate system calibration is paramount for optimum performance. Narrowband systems which implement beamforming via attenuators and phase shifters often employ lookup tables (LUT) containing a set of correction commands to be superimposed on the desired steering operation. These are commonly dependent on current and desired system characteristics, such as operating frequency, steering direction, power level, and/or temperature conditions. In contrast, wideband systems require higher fidelity compensation techniques capable of correcting imbalanced and dispersive channel effects from element-level electronics. This dissertation examines deterministic and adaptive beamforming techniques and provides solutions to the aforementioned challenges by contributing the development and demonstration of a wideband digital beamformer with equalization on an RF system-on-a-chip (RFSoC). Performance metrics of the testbed match or exceed current publications of RFSoC based demonstrations. The RFSoC is a unique, state-of-the-art, highly integrated device that incorporates a field programmable gate array (FPGA), high speed ADCs and DACs with a system-on-a-chip (SOC) architecture onto the same silicon fabric. As much of the digital and analog RF circuitry is now integrated into a single package, these devices are revolutionizing radar and communication systems, reshaping phased array system design strategies. This enabling technology facilitates the development of compact all-digital arrays, massively increasing the available degrees of freedom in system control, a paradigm shift in industry and engineering communities. The beamformer testbed is demonstrated on a sub-Nyquist-sampled 1.6 GHz S-band phased array system implemented using a Xilinx 8-channel 4 GSPS RFSoC. To enable TTD digital beamsteering, each channel is compensated via a conjugate symmetric fractional-sample delay FIR filter bank. By modifying the TTD filter structure to support complex coefficients, channel equalization is integrated with the fractional-sample delays to compensate undesired channel characteristics. To confirm the efficacy of this approach, results are provided for uncalibrated and calibrated system operation. Anechoic chamber measurements are presented as well as the FPGA floorplans showing RFSoC device utilization for both uncalibrated and calibrated configurations