6 GHz RF CMOS Active Inductor Band Pass Filter Design and Process Variation Detection

A 90nm CMOS active inductor band pass filter with automatic peak detection is demonstrated in this thesis. The active inductor band pass filter has a better performance than the passive band pass filter in on-chip circuit design, due to small area, larger gain and tunable frequency. However, process variation makes the active inductor band pass filter hard to be used widely in many applications. To settle this issue, an automatic voltage peak detector is introduced to detect the process variation direction and hope to be used to control the active inductor band pass filter center frequency and gain. The designed active filter shows center frequency of 6GHz and quality factor (Q) of 31.9. To drive the peak detector, two analog buffers are designed with f-dB over 6GHz, and one has 0dB gain at low frequency region, another one would emphasize 0dB gain on 6GHz. The voltage peak detector can detect the AC input amplitude range from 0.06V to 0.6 and produce a linear output DC voltage of 77.97mV to 726.65mV

Techniques for Frequency Synthesizer-Based Transmitters.

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113385/1/mammad_1.pd

A 30 Gb/s CMOS driver integrated with silicon photonics MZM

A voltage mode modulator driver is proposed in the TSMC 65nm low power CMOS process. In the electrical testing, the driver itself can achieve a bit rate of 40Gb/s with the single-ended output swing of 1.65V. Unlike equivalent CML modulator drivers, when the proposed driver is integrated with the silicon photonic MZM, it does not require an additional biasing network. The integrated electro-optic transmitter can achieve 30Gb/s with an extinction ratio of 4.05dB, with the power consumption of main driver being 323mW

Fully integrated cmos phase shifter/vco for mimo/ism application

A fully integrated CMOS 0 – 900 phase shifter in 0.18um TSMC technology is presented. With the increasing use of wireless systems in GHz range, there is high demand for integrated phase shifters in phased arrays and MIMO on chip systems. Integrated phase shifters have quite a high number of integrated inductors which consume a lot of area and introduce a huge amount of loss which make them impractical for on chip applications. Also tuning the phase shift is another concern which seems difficult with use of passive elements for integrated applications. This work is presents a new method for implementing phase shifters using only active CMOS elements which dramatically reduce the occupied area and make the tuning feasible. Also a fully integrated millimeter-wave VCO is implemented using the same technology. This VCO can be part of a 24 GHz frequency synthesizer for 24 GHz ISM band transceivers. The 24 GHz ISM band is the unlicensed band and available for commercial communication and automotive radar use, which is becoming attractive for high bandwidth data rate

Architecture for ultra-low power multi-channel transmitters for Body Area Networks using RF resonators

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 99-103).Body Area Networks (BANs) are gaining prominence for their use in medical and sports monitoring. This thesis develops the specifications of a ultra-low power 2.4GHz transmitter for use in a Body Area Networks, taking advantage of the asymmetric energy constraints on the sensor node and the basestation. The specifications include low transmit output powers, around -10dBm, low startup time, simple modulation schemes of OOK, FSK and BPSK and high datarates of 1Mbps. An architecture that is suited for the unique requirements of transmitters in these BANs is developed. RF Resonators, and in particular Film Bulk Acoustic Wave Resonators (FBARs) are explored as carrier frequency generators since they provide stable frequencies without the need for PLLs. The frequency of oscillation is directly modulated to generate FSK. Since these oscillators have low tuning range, the architecture uses multiple resonators to define the center frequencies of the multiple channels. A scalable scheme that uses a resonant buffer is developed to multiplex the oscillators' outputs to the Power Amplifier (PA). The buffer is also capable of generating BPSK signals. Finally a PA optimized for efficiently delivering the low output powers required in BANs is developed. A tunable matching network in the PA also enables pulse-shaping for spectrally efficient modulation. A prototype transmitter supporting 3 FBAR-oscillator channels in the 2.4GHz ISM band was designed in a 65nm CMOS process. It operates from a 0.7V supply for the RF portion and 1V for the digital section. The transmitter achieves 1Mbps FSK, up to 10Mbps for OOK and BPSK without pulse shaping and 1Mbps for OOK and BPSK with pulse shaping. The power amplifier has an efficiency of up to 43% and outputs between -15dBm and -7.5dBm onto a 50Q antenna. Overall, the transmitter achieves an efficiency of upto 26% and energy per bit of 483pJ/bit at 1Mbps.by Arun Paidimarri.S.M

Design of VCOs in Deep Sub-micron Technologies

This work will present a more accurate frequency prediction model for single-ended ring oscillators (ROs), a case-study comparing different ROs, and a design method for LC voltage-controlled oscillators (LCVCOs) that uses a MATLAB script based on analytical equations to output a graphical design space showing performance characteristics as a function of design parameters. Using this method, design trade-offs become clear, and the designer can choose which performance characteristics to optimize. These methods were used to design various topologies of ring oscillators and LCVCOs in the GlobalFoundries 28 nm HPP CMOS technology, comparing the performance between different topologies based on simulation results. The results from the MATLAB design script were compared to simulation results as well to show the effectiveness of the design methods. Three varieties of 5 GHz voltage controlled ring oscillators were designed in the GlobalFoundries 28 nm HPP CMOS technology. The first is a low current low dropout regulator (LDO) tuned ring oscillator designed with thin oxide devices and a 0.85 V supply. The second is a high current LDO-tuned ring oscillator designed with medium oxide devices and a 1.5 V supply. The third is varactor-tuned ring oscillator with no LDO, and 0.85 V supply. Performance comparison of these ring oscillator systems are presented, outlining trade-offs between tuning range, phase noise, power dissipation, and area. The varactor-tuned ring oscillator exhibits 8.89 dBc/Hz (with power supply noise) and 16.27 dBc/Hz (without power supply noise) improvement in phase noise over the best-performing LDO-tuned ring oscillator. There are advantages in average power dissipation and area for a minimal tradeoff in tuning range with the varactor-tuned ring oscillator. Four multi-GHz LCVCOs were designed in the GlobalFoundries 28 nm HPP CMOS technology: 15 GHz varactor-tuned NMOS-only, 9 GHz varactor-tuned self-biased CMOS, 14.2 GHz digitally-tuned NMOS-only, and 8.2 GHz digitally-tuned self-biased CMOS. As a design method, analytical ex-pressions describing tuning range, tank amplitude constraint, and startup condition were used in MATLAB to output a graphical view of the design space for both NMOS-only and CMOS LCVCOs, with maximum varactor capacitance on the y-axis and NMOS transistor width on the x-axis. Phase noise was predicted as well. In addition to the standard varactor control voltage tuning method, digitally-tuned implementations of both NMOS and CMOS LCVCOs are presented. The performance aspects of all designed LCVCOs are compared. Both varactor-tuned and digitally-tuned NMOS LCVCOs have lower phase noise, lower power consumption, and higher tuning range than both CMOS topologies. The varactor-tuned NMOS LCVCO has the lowest phase noise of -97 dBc/Hz at 1 MHz offset from 15 GHz center frequency, FOM of -172.20 dBc/Hz, and FOMT of -167.76 dBc/Hz. The digitally-tuned CMOS LCVCO has the greatest tuning range at 10%. Phase noise is improved by 3 dBc/Hz with the digitally-tuned CMOS topology over varactor-tuned CMOS

Digital Phase Locked-Loop With Wide Tuning Range And Dynamic Phase Shift

For decades, Phase Lock Loop (PLL) has been widely used in numerous systems, such as telecommunications and digital design, where it plays significant role in improving overall system timing. Moving forward, with the latest revolution towards System-on-chip technology (SOC), the need of PLL in the form of Integrated Circuits has been growing tremendously. Core of this research is to design a PLL with wide tuning range and dynamic phase shift feature, which is implemented in the Integrated Circuits level. In line with fierce competition and fast-paced semiconductor industry, PLL design with above features are definitely most sought after, as it will tremendously reduce turn-around time, cost and effort for a project. Wide tuning range is achieved by introducing new Voltage Control Oscillator architecture, which will be able to provide wide tuning range without using very high KVCO. The new architecture proposed in this project is in differential input structure and consists of MOSFETs and capacitors; thus the area of implementation is small.Besides, extra feature which is proposed in this PLL is Dynamic Phase Shift feature. Dynamically tunable phase shift is important since the accuracy of the phase could be adjusted without having to reprogram the PLL, thus saving a lot of time. Dynamic Phase Shift feature is a new idea, which its design is implemented by using UP/DOWN counters, OR and AND gates. The complete design includes synchronous system design work such as state machine, diagram and truth table for system simplification. This proposed design achieved all specifications with wide-tuning range of 600MHz to 1300MHz is achieved with control voltage swing of 0.9V to 1.5V. Besides, the maximum static phase error measured in the simulation is 66ps, which is smaller than 200ps specification. Highest Period Jitter is 181ps while Cycle-to-Cycle Jitter is 55ps. Both types of jitter are within specification; lower than 300ps. Dynamic Phase Shift also successfully implemented where the UP/DN signal as the control to indicate either the phase is to be shifted up or down

Ultra-low power RF receiver based on double-gate CMOS FinFET technology

In this research, design approaches and methodologies were presented to realize the ultra-low power RF receiver front-end circuits. Moderate inversion operation was explored as a possible method of reducing power consumption along with the use of low supply voltage. The research is firstly concentrated on passive and active devices modeling. One of the most commonly used passive devices is on-chip inductor. On-chip spiral inductor model was developed firstly. Compared to the model developed by others, this model can predict the behavior of the inductors with different structural parameters over a board frequency range (from 0.1 to 10 GHz). Then the SOI varactor model was developed based on our measurement and extraction.Besides the passive devices modeling, a new most promising MOSFET candidate, FinFET, was characterized at GHz frequency range. Based on the measurement results, we found the FinFET transistors did have superior performance over bulk-Si CMOS technology. And an RF circuit model of FinFET was developed followed that, which was published in Electronics Letters. To my best knowledge, this was the first RF FinFET model published world wide at that time. It provides the basic idea about how to model this new structure MOSFET.Based on the passive and active device models developed, Global Positioning System (GPS) receiver front end circuits were designed and measured. Comparing to the previous designs with the same constrains, the ultra-low power GPS receiver building block circuits in this research have much less power consumption than the best design published before

Design and Implementation of a Low‐Power Wireless Respiration Monitoring Sensor

Wireless devices for monitoring of respiration activities can play a major role in advancing modern home-based health care applications. Existing methods for respiration monitoring require special algorithms and high precision filters to eliminate noise and other motion artifacts. These necessitate additional power consuming circuitry for further signal conditioning. This dissertation is particularly focused on a novel approach of respiration monitoring based on a PVDF-based pyroelectric transducer. Low-power, low-noise, and fully integrated charge amplifiers are designed to serve as the front-end amplifier of the sensor to efficiently convert the charge generated by the transducer into a proportional voltage signal. To transmit the respiration data wirelessly, a lowpower transmitter design is crucial. This energy constraint motivates the exploration of the design of a duty-cycled transmitter, where the radio is designed to be turned off most of the time and turned on only for a short duration of time. Due to its inherent duty-cycled nature, impulse radio ultra-wideband (IR-UWB) transmitter is an ideal candidate for the implementation of a duty-cycled radio. To achieve better energy efficiency and longer battery lifetime a low-power low-complexity OOK (on-off keying) based impulse radio ultra-wideband (IR-UWB) transmitter is designed and implemented using standard CMOS process. Initial simulation and test results exhibit a promising advancement towards the development of an energy-efficient wireless sensor for monitoring of respiration activities

Design of an Active Harmonic Rejection N-Path Filter for Highly Tunable RF Channel Selection

As the number of wireless devices in the world increases, so does the demand for flexible radio receiver architectures capable of operating over a wide range of frequencies and communication protocols. The resonance-based channel-select filters used in traditional radio architectures have a fixed frequency response, making them poorly suited for such a receiver. The N-path filter is based on 1960s technology that has received renewed interest in recent years for its application as a linear high Q filter at radio frequencies. N-path filters use passive mixers to apply a frequency transformation to a baseband low-pass filter in order to achieve a high-Q band-pass response at high frequencies. The clock frequency determines the center frequency of the band-pass filter, which makes the filter highly tunable over a broad frequency range. Issues with harmonic transfer and poor attenuation limit the feasibility of using N-path filters in practice. The goal of this thesis is to design an integrated active N-path filter that improves upon the passive N-path filter’s poor harmonic rejection and limited outof- band attenuation. The integrated circuit (IC) is implemented using the CMRF8SF 130nm CMOS process. The design uses a multi-phase clock generation circuit to implement a harmonic rejection mixer in order to suppress the 3rd and 5th harmonic. The completed active N-path filter has a tuning range of 200MHz to 1GHz and the out-ofband attenuation exceeds 60dB throughout this range. The frequency response exhibits a 14.7dB gain at the center frequency and a -3dB bandwidth of 6.8MHz