2 research outputs found
Contribution to time domain readout circuits design for multi-standard sensing system for low voltage supply and high-resolution applications
Mención Internacional en el título de doctorThis research activity has the purpose of open new possibilities in the design of capacitance-to-digital converters (CDCs) by developing a solution based on time domain conversion. This can be applied to applications related with the Internet-of-Things (IoT). These applications are present in any electronic devices where sensing is needed. To be able to reduce the area of the whole system with the required performance, micro-electromechanical systems (MEMS) sensors are used in these applications. We propose a new family of sensor readout electronics to be integrated with MEMS sensors.
Within the time domain converters, Dual Slope (DS) topology is very interesting to explore a new compromise between performances, area and power consumption. DS topology has been extensively used in instrumentation. The simplicity and robustness of the blocks inside classical DS converters it is the main advantage. However, they are not efficient for applications where higher bandwidth is required. To extend the bandwidth, DS converters have been introduced into ΔΣ loops. This topology has been named as integrating converters. They increase the bandwidth compare to classical DS architecture but at the expense of higher complexity. In this work we propose the use of a new family of DS converters that keep the advantages of the classical architecture and introduce noise shaping. This way the bandwidth is increased without extra blocks. The Self-Compensated noise-shaped DS converter (the name given to the new topology) keeps the signal transfer function (STF) and the noise transfer function (NTF) of Integrating converters. However, we introduce a new arrangement in the core of the converter to do noise shaping without extra circuitry. This way the simplicity of the architecture is preserved.
We propose to use the Self-Compensated DS converter as a CDC for MEMS sensors. This work makes a study of the best possible integration of the two blocks to keep the signal integrity considering the electromechanical behavior of the sensor.
The purpose of this front-end is to be connected to any kind of capacitive MEMS sensor. However, to prove the concepts developed in this thesis the architecture has been connected to a pressure MEMS sensor.
An experimental prototype was implemented in 130-nm CMOS process using the architecture mentioned before. A peak SNR of 103.9 dB (equivalent to 1Pa) has been achieved within a time measurement of 20 ms. The final prototype has a power consumption of 220 μW with an effective area of 0.317 mm2. The designed architecture shows good performance having competitive numbers against high resolution topologies in amplitude domain.Esta actividad de investigación tiene el propósito de explorar nuevas posibilidades en el diseño de convertidores de capacitancia a digital (CDC) mediante el desarrollo de una solución basada en la conversión en el dominio del tiempo. Estos convertidores se pueden utilizar en aplicaciones relacionadas con el mercado del Internet-de-las-cosas (IoT). Hoy en día, estas aplicaciones están presentes en cualquier dispositivo electrónico donde se necesite sensar una magnitud. Para poder reducir el área de todo el sistema con el rendimiento requerido, se utilizan sensores de sistemas micro-electromecánicos (MEMS) en estas aplicaciones. Proponemos una nueva familia de electrónica de acondicionamiento para integrar con sensores MEMS.
Dentro de los convertidores de dominio de tiempo, la topología del doble-rampa (DS) es muy interesante para explorar un nuevo compromiso entre rendimiento, área y consumo de energía. La topología de DS se ha usado ampliamente en instrumentación. La simplicidad y la solidez de los bloques dentro de los convertidores DS clásicos es la principal ventaja. Sin embargo, no son eficientes para aplicaciones donde se requiere mayor ancho de banda. Para ampliar el ancho de banda, los convertidores DS se han introducido en bucles ΔΣ. Esta topología ha sido nombrada como Integrating converters. Esta topología aumenta el ancho de banda en comparación con la arquitectura clásica de DS, pero a expensas de una mayor complejidad. En este trabajo, proponemos el uso de una nueva familia de convertidores DS que mantienen las ventajas de la arquitectura clásica e introducen la configuración del ruido. De esta forma, el ancho de banda aumenta sin bloques adicionales. El convertidor Self-Compensated noise-shaped DS (el nombre dado a la nueva topología) mantiene la función de transferencia de señal (STF) y la función de transferencia de ruido (NTF) de los Integrating converters. Sin embargo, presentamos una nueva topología en el núcleo del convertidor para conformar el ruido sin circuitos adicionales. De esta manera, se preserva la simplicidad de la arquitectura.
Proponemos utilizar el Self-Compensated noise-shaped DS como un CDC para sensores MEMS. Este trabajo hace un estudio de la mejor integración posible de los dos bloques para mantener la integridad de la señal considerando el comportamiento electromecánico del sensor.
El propósito de este circuito de acondicionamiento es conectarse a cualquier tipo de sensor MEMS capacitivo. Sin embargo, para demostrar los conceptos desarrollados en esta tesis, la arquitectura se ha conectado a un sensor MEMS de presión.
Se ha implementado dos prototipos experimentales en un proceso CMOS de 130-nm utilizando la arquitectura mencionada anteriormente. Se ha logrado una relación señal-ruido máxima de 103.9 dB (equivalente a 1 Pa) con un tiempo de medida de 20 ms. El prototipo final tiene un consumo de energía de 220 μW con un área efectiva de 0.317 mm2. La arquitectura diseñada muestra un buen rendimiento comparable con las arquitecturas en el dominio de la amplitud que muestran resoluciones equivalentes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Pieter Rombouts.- Secretario: Alberto Rodríguez Pérez.- Vocal: Dietmar Strãußnig
An all-digital charge to digital converter
PhD ThesisDuring the last two decades, the topic of the Internet of Things
(IoT) has become very popular. It provides an idea that everything
in the real world should be connected with the internet
in the future. Integrating sensors into small wireless networked
nodes is a huge challenge due to the low power/energy budget
in wireless sensor systems. An integrated sensor normally
consumes significant power and has complex design which increases
the cost. The core part of the sensor is the sensor interface
which consumes major power especially for a capacitor-based
sensor.
Capacitive sensors and voltage sensors are two frequently
used sensor types in the wireless sensor family. Capacitive sensors,
that transform capacitance values into digital outputs, can
be used in areas such as biomedical, environmental, and mobile
applications. Voltage sensors are also widely used in many modern
areas such as Energy Harvesting (EH) systems. Both of these
sensors may make use of sensor interfaces to transform a measured
analogue signal into a frequency output or a digital code
for use in a digital system. Existing sensor interfaces normally
use complex analog-to-digital converter (ADC) techniques that
consume high power and suffers from slow sensing response.
This thesis proposes a smart all-digital dual-use capacitorbased
sensor interface called charge to digital converter (QDC).
This QDC is capable of not only sensing capacitance but also
sensing voltages by using fully digital solutions based on iterative
delay chain discharge. Unlike the conventional methods
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that only treats the sensed capacitance only as the input signal,
this thesis proposes a method that can directly use the stored
energy from the sensed capacitance as well to power parts of
the circuit, which simplifies the design and saves power. By
playing with the capacitance and input voltage, it can be used
as a capacitance-to-digital converter (CDC) to sense capacitance
under fixed input voltage and it also can be used as a capacitorbased
voltage sensor interface to measure voltage level under
fixed capacitance. The new method achieves the same accuracy
with less than half the circuit size, and 25% and 33% savings on
power and energy consumption compared with the state of art
benchmark. The method has been validated by experimenting
with a chip fabricated in 350nm process, in addition to extensive
simulation analysis