Receiver architecture of the thousand-element array (THEA)

As part of the development of a new international radio-telescope SKA (Square Kilometre Array), an outdoor phasedarray prototype, the THousand Element Array (THEA), is being developed at NFRA. THEA is a phased array with 1024 active elements distributed on a regular grid over a surface of approximately 16 m2. The array is organised into 16 units denoted as tiles. THEA operates in the frequency band from 750 to 1500 MHz.\ud On a tile the signals from 64 antenna elements are converted into two independent RF beams. Two times 16 beams can be made simultaneously with full sensitivity by the real-time digital beam former of the THEA system. At the output of each tile the analog RF signal from a beam is converted into a 2 × 12-bit digital quadrature representation by a receiver system.\ud A double super-heterodyne architecture is used to mix the signal band of interest to an intermediate frequency of 210 MHz. The IF-signal is shifted to baseband by means of a partly digitally implemented I/Q mixer scheme. After a quadrature mixer stage, the I and Q signals are digitised by means of 12 bit A/D converters at 40 MS/s. Implementing a part of the mixing scheme digitally offers the flexibility to use different I/Q architectures, e.g. Hartley and Weaver mixer setups. This way the effect of RFI in different mixing architectures can be analyzed. After the digital processing, the samples are multiplexed, serialised and transported over fibres to the central adaptive digital beam former unit where the signals from all tiles are combined giving 32 beams.\ud This paper focuses on the design choices and the final implementation of the THEA system. In particular, the receiver architecture is addressed. A digital solution is presented, which enables switching between a Hartley and a Weaver based mixer scheme

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios

Dual Mode Suspended Substrate Stripline (SSS) Filter

Evolution of wireless communication systems towards high flexibility, low cost and high efficiency leads to tremendous activity in the area of microwave filters. In an RF front-end of a cellular radio base station, signals are being transmitted and received simultaneously. In the receive band, there are chances of intermodulation products from the power amplifier being fed to the receiver,thus the transmit filter must have a very high level of signal rejection. Furthermore, the transmit filter must also have low passband insertion loss since it impacts the power transmitted and the overall transmit system efficiency. Recently, filters with dual-mode operation were being investigated due to their ability to produce two degenerate modes using a single physical structure; therefore, the size and cost of the filter can be reduced without compromising any figure-of-merits. A dual mode suspended substrate stripline filter is presented in this thesis. These filters enable achieving low insertion loss, high Q, high selectivity and good spurious response. Initially, a dual mode ring resonator structure is investigated using suspended substrate stripline technology. This technology is used due to its advantages which are comparable to microstrip or any other planar transmission lines. The HFSS three dimensional finite element method (FEM) is used to evaluate the resonant frequency, quality factor and the first harmonics.A second order suspended substrate stripline filter was designed with capacitive coupled input and output feeding method. The input and output feed were positioned 90 degree from each other while a notch was used in this filter to couple two degenerate modes which also control the bandwidth of the filter. A high performance Generalized Chebychev filter was designed to meet the stringent electrical requirement in the RF front-end of a cellular radio base station. With this fourth order filter, four finite frequency transmission zeros were achieved due to phase cancellation between two paths which results in high selectivity filter response. Metal tuning screws were added to improve any practical imperfections. Finally an asymmetrical Generalized Chebychev filter was designed with real frequency transmission zeros positioned on one side of the passband. With this design, the aim of achieving higher selectivity filter response above the passband was demonstrated

Development of a broadband and squint-free Ku-band phased array antenna system for airborne satellite communications

Novel avionic communication systems are required for various purposes, for example to increase the flight safety and operational integrity as well as to enhance the quality of service to passengers on board. To serve these purposes, a key technology that is essential to be developed is an antenna system that can provide broadband connectivity within aircraft cabins at an affordable price. Currently, in the European Commission (EC) 7th Framework Programme SANDRA project (SANDRA, 2011), a development of such an antenna system is being carried out. The system is an electronically-steered phased-array antenna (PAA) with a low aerodynamic profile. The reception of digital video broadcasting by satellite (DVB-S) signal which is in the frequency range of 10.7-12.75 GHz (Ku-band) is being considered. In order to ensure the quality of service provided to the passengers, the developed antenna should be able to receive the entire DVB-S band at once while complying with the requirements of the DVB-S system (Morello & Mignone, 2006). These requirements, as will be explained later, dictate a broadband antenna system where the beam is squint-free, i.e. no variation of beam pointing direction for all the frequencies in the desired band. Additionally, to track the satellite, the seamless tunability of the beam pointing direction of this antenna is also required. In this work, a concept of optical beamforming (Riza & Thompson, 1997) is implemented to provide a squint-free beam over the entire Ku-band for all the desired pointing directions. The optical beamformer itself consists of continuously tunable optical delay lines that enable seamless tunability of the beam pointing direction

Highly Linear Filtering TIA for 5G wireless standard and beyond

The demand for high data rates in emerging wireless standards is a result of the growing number of wireless device subscribers. This demand is met by increasing the channel bandwidth in accordance with historical trends. As MIMO technology advances, more bands and antennas are expected to be used. The most recent 5G standard makes use of mm-wave bands above 24GHz to expand the channel bandwidth. Channel bandwidth can exceed 2GHz when carrier aggregation is used. From the receiver’s point of view, this makes the baseband filter’s design, which is often a TIA, more difficult. This is due to the fact that as the bandwidth approaches the GHz range, the TIA’s UGBW should be more than 5GHz and it should have a high loop gain up to high frequencies. A closed-loop TIA with configurable bandwidth up to 1.5GHz is described in this scenario. Operational Transconductance Amplifier (OTA) closed in shunt-feedback is the foundation of the TIA. The proposed OTA is based on FeedForward topology (FF) together with inductive peaking technique to ensure stability rather than using the traditional Miller compensation technique. The TIA is able to produce GLoop unity gain bandwidth of 7.5GHz and high loop gain (i.e. 27dB @ 1GHz) using this method. The mixer and LNA’s linearity will benefit from this. Utilizing TSMC 28nm CMOS technology, a prototype has been created using this methodology. The output integrated noise from 20MHz to 1.5GHz is lower than 300μVrms with a power consumption of 17mW, and the TIA achieves In-band OIP3 of 33dBm. Additionally, a direct-conversion receiver for 5G applications is described. The 7GHz RF signal is down-converted to baseband by the receiver. Two cascaded LNTAs based on a common-gate transformer-based design make up the frontend. With an RF gain of 80mS and a gain variability of 31dB, it provides wideband matching from 6GHz to 8GHz. A double-balanced passive mixer is driven by the LNTA. The channel bandwidth from 50MHz to 2GHz is covered by two baseband paths. The first path, called as the low frequency path (LF), covers the channel bandwidth ranging from 50MHz to 400 MHz. In contrast, the second path, called as the high frequency path (HF), covers the channel bandwidth between 800MHz and 2GHz. Two baseband provide gain variability of 14dB, making the overall receiver able to have a gain configurability from 45dB to 0dB. Out-of-band (OOB) selectivity at 4 times the band-edge is greater than 33dB for each configurability. When the gain is at its maximum, the noise figure is less than 5.8dB, and the slope of the noise rise as the gain falls is less than 0.7dB/dB. The receiver guarantee an IB-OIP3 larger than 21dBm for any gain configuration. The receiver has been implemented in TSMC 28nm CMOS technology, consuming 51mW for LF path and 68mW for HF path. The measurement results are in perfect accordance with the requirements of the design

Configurable circuits and their impact on multi-standard RF front-end architectures

This thesis studies configurable circuits and their impact on multi-standard RF front-end architectures. In particular, low-voltage low-power linear LNA and mixer topologies suitable for implementation in multi-standard front-ends are subject of the investigation. With respect to frequency and bandwidth, multi-standard front-ends can be implemented using either tunable or wideband LNA and mixer topologies. Based on the type of the LNA and mixer(s), multi-standard receiver RF front-ends can be divided into three groups. They can be (tunable) narrow-band, wide-band or combined. The advantages and disadvantages of the different multi-standard receiver RF front-ends have been discussed in detail. The partitioning between off-chip selectivity, on-chip selectivity provided by the LNA and mixer, linearity, power consumption and occupied chip area in each multi-standard RF front-end group are thoroughly investigated. A Figure of Merit (FOM) for the multi-standard receiver RF front-end has been introduced. Based on this FOM the most suitable multi-standard RF front-end group in terms of cost-effectiveness can be selected. In order to determine which multi-standard RF front-end group is the most cost-effective for a practical application, a GSM850/E-GSM/DCS/PCS/Bluetooth/WLANa/b/g multi-standard receiver RF front-end is chosen as a demonstrator. These standards are the most frequently used standards in wireless communication, and this combination of standards allows to users almost "anytime-anywhere" voice and data transfer. In order to verify these results, three demonstrators have been defined, designed and implemented, two wideband RF front-end circuits in 90nm CMOS and 65nm CMOS, and one combined multi-standard RF front-end circuit in 65nm CMOS. The proposed multi-standard demonstrators have been compared with the state-of the art narrow-band, wide-band and combined multi-standard RF front-ends. On the proposed multi-standard RF front-ends and the state-of the art multi-standard RF front-ends the proposed FOM have been applied. The comparison shows that the combined multi-standard RF front-end group is the most cost effective multi-standard group for this application

Design of a Microstrip Bandpass Filter for 3.1-10.6 GHz Uwb Systems

In this thesis, ultra-wideband (UWB) microwave filters and design challenges are studied and, a microstrip UWB filter prototype design is presented. The UWB bandpass filter operating in the 3.6 GHz to 10.6 GHz frequency band is targeted to comply with the FCC spectral mask for UWB systems. The prototype filter is composed of quarter-wavelength spaced shunt stub transmission lines. The circuit is first simulated and optimized by using AWR DE simulation software tool. Then Sonnet EM Simulation and CST EM Simulation Tools are further utilized to obtain more accurate simulated results. The fabricated microstrip UWB bandpass filter is then measured using a vector network analyzer and results are presented. The prototype built can be used in UWB communications or localization systems

Interference-robust CMOS receivers for IoT:Highly linear RF front-ends at low power

Wireless technologies have brought Internet access to more than half of the world’s population in the last decade. Nowadays, Internet-of-Things (IoT) technology extends the internet connectivity to sensor nodes embedded in machines, animals, and plants. It will soon put us in a realm of billions of interconnected sensor nodes networking and communicating with each other. Such unprecedented growth of wireless devices puts a big challenge of sustainable and robust connectivity in front of us. Concretely, this challenge demands a wireless sensor node with low power and robust connectivity. Radios are the physical interface for sensor nodes with the external world and are one of the power-hungry components in sensor nodes. Hence it is imperative to make them energy-efficient and interference-robust. This thesis explores CMOS passive mixer-first receiver topology to enhance the interference tolerance of receivers in IoT radios. The dissertation proposes a novel N-path filter/mixer topology at the circuit level and a multipath cross-correlation technique at the system level. Two test-chips of mixer-first receiver front ends, using these techniques, are implemented in CMOS FDSOI 22nm technology as a proof-of-concept. The experimental prototypes demonstrate voltage gain in passive mixers and exhibit high-Q widely-tunable RF filtering, large out-of-band and harmonic interferer tolerance, and moderate noise figure while consuming much lower power than several state-of-the-art receivers

Efficient and Interference-Resilient Wireless Connectivity for IoT Applications

With the coming of age of the Internet of Things (IoT), demand on ultra-low power (ULP) and low-cost radios will continue to boost tremendously. The Bluetooth-Low-energy (BLE) standard provides a low power solution to connect IoT nodes with mobile devices, however, the power of maintaining a connection with a reasonable latency remains the limiting factor in defining the lifetime of event-driven BLE devices. BLE radio power consumption is in the milliwatt range and can be duty cycled for average powers around 30μW, but at the expense of long latency. Furthermore, wireless transceivers traditionally perform local oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Innovations in both the system architecture and circuits implementation are essential for the design of truly ubiquitous receivers for IoT applications. This research presents two porotypes as back-channel BLE receivers, which have lower power consumption while still being robust in the presents of interference and able to receive back-channel message from BLE compliant transmitters. In addition, the first crystal-less transmitter with symmetric over-the-air clock recovery compliant with the BLE standard using a GFSK-Modulated BLE Packet is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162942/1/abdulalg_1.pd