A 0.01mm2, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification

A reconfigurable, high-impedance, DC-coupled low-frequency digital acquisition front-end (DAFE) suitable to operate under a power supply voltage ranging from 0.2 to IV down to 600 pW power is presented in this paper. Matching-indifferent DC accuracy over a rail-to-rail input range is uniquely achieved by the new time-multiplexed digital differential amplification technique at ultra-low area and without chopping and auto-zeroing. A 180 nm testchip of the proposed DAFE occupies 0.00945 mm 2 and draws 4.5 nW at a 0.4 V supply, has a 120 Hz gain-bandwidth product, with an in-band input noise of 11.3 µV r ms , a 137 µV input offset voltage standard deviation, 65.7dB CMRR, 63.8dB PSRR, and provides a 46.5dB-SFDR, 6.9 bit-ENOB digitized output at -12 dBFS

Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.

Understanding dynamics of the brain has tremendously improved due to the progress in neural recording techniques over the past five decades. The number of simultaneously recorded channels has actually doubled every 7 years, which implies that a recording system with a few thousand channels should be available in the next two decades. Nonetheless, a leap in the number of simultaneous channels has remained an unmet need due to many limitations, especially in the front-end recording integrated circuits (IC). This research has focused on increasing the number of simultaneously recorded channels and providing modular design approaches to improve the integration and expansion of 3-D recording microsystems. Three analog front-ends (AFE) have been developed using extremely low-power and small-area circuit techniques on both the circuit and system levels. The three prototypes have investigated some critical circuit challenges in power, area, interface, and modularity. The first AFE (16-channels) has optimized energy efficiency using techniques such as moderate inversion, minimized asynchronous interface for data acquisition, power-scalable sampling operation, and a wide configuration range of gain and bandwidth. Circuits in this part were designed in a 0.25μm CMOS process using a 0.9-V single supply and feature a power consumption of 4μW/channel and an energy-area efficiency of 7.51x10^15 in units of J^-1Vrms^-1mm^-2. The second AFE (128-channels) provides the next level of scaling using dc-coupled analog compression techniques to reject the electrode offset and reduce the implementation area further. Signal processing techniques were also explored to transfer some computational power outside the brain. Circuits in this part were designed in a 180nm CMOS process using a 0.5-V single supply and feature a power consumption of 2.5μW/channel, and energy-area efficiency of 30.2x10^15 J^-1Vrms^-1mm^-2. The last AFE (128-channels) shows another leap in neural recording using monolithic integration of recording circuits on the shanks of neural probes. Monolithic integration may be the most effective approach to allow simultaneous recording of more than 1,024 channels. The probe and circuits in this part were designed in a 150 nm SOI CMOS process using a 0.5-V single supply and feature a power consumption of only 1.4μW/channel and energy-area efficiency of 36.4x10^15 J^-1Vrms^-1mm^-2.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98070/1/ashmouny_1.pd

Nano-Watt Modular Integrated Circuits for Wireless Neural Interface.

In this work, a nano-watt modular neural interface circuit is proposed for ECoG neuroprosthetics. The main purposes of this work are threefold: (1) optimizing the power-performance of the neural interface circuits based on ECoG signal characteristics, (2) equipping a stimulation capability, and (3) providing a modular system solution to expand functionality. To achieve these aims, the proposed system introduces the following contributions/innovations: (1) power-noise optimization based on the ECoG signal driven analysis, (2) extreme low-power analog front-ends, (3) Manchester clock-edge modulation clock data recovery, (4) power-efficient data compression, (5) integrated stimulator with fully programmable waveform, (6) wireless signal transmission through skin, and (7) modular expandable design. Towards these challenges and contributions, three different ECoG neural interface systems, ENI-1, ENI-16, and ENI-32, have been designed, fabricated, and tested. The first ENI system(ENI-1) is a one-channel analog front-end and fabricated in a 0.25µm CMOS process with chopper stabilized pseudo open-loop preamplifier and area-efficient SAR ADC. The measured channel power, noise and area are 1.68µW at 2.5V power-supply, 1.69µVrms (NEF=2.43), and 0.0694mm^2, respectively. The fabricated IC is packaged with customized miniaturized package. In-vivo human EEG is successfully measured with the fabricated ENI-1-IC. To demonstrate a system expandability and wireless link, ENI-16 IC is fabricated in 0.25µm CMOS process and has sixteen channels with a push-pull preamplifier, asynchronous SAR ADC, and intra-skin communication(ISCOM) which is a new way of transmitting the signal through skin. The measured channel power, noise and area are 780nW, 4.26µVrms (NEF=5.2), and 2.88mm^2, respectively. With the fabricated ENI-16-IC, in-vivo epidural ECoG from monkey is successfully measured. As a closed-loop system, ENI-32 focuses on optimizing the power performance based on a bio-signal property and integrating stimulator. ENI-32 is fabricated in 0.18µm CMOS process and has thirty-two recording channels and four stimulation channels with a cyclic preamplifier, data compression, asymmetric wireless transceiver (Tx/Rx). The measured channel power, noise and area are 140nW (680nW including ISCOM), 3.26µVrms (NEF=1.6), and 5.76mm^2, respectively. The ENI-32 achieves an order of magnitude power reduction while maintaining the system performance. The proposed nano-watt ENI-32 can be the first practical wireless closed-loop solution with a practically miniaturized implantable device.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98064/1/schang_1.pd

Integrated circuit design for implantable neural interfaces

Progress in microfabrication technology has opened the way for new possibilities in neuroscience and medicine. Chronic, biocompatible brain implants with recording and stimulation capabilities provided by embedded electronics have been successfully demonstrated. However, more ambitious applications call for improvements in every aspect of existing implementations. This thesis proposes two prototypes that advance the field in significant ways. The first prototype is a neural recording front-end with spectral selectivity capabilities that implements a design strategy that leads to the lowest reported power consumption as compared to the state of the art. The second one is a bidirectional front-end for closed-loop neuromodulation that accounts for self-interference and impedance mismatch thus enabling simultaneous recording and stimulation. The design process and experimental verification of both prototypes is presented herein

Study, optimization and silicon implementation of a smart high-voltage conditioning circuit for electrostatic vibration energy harvesting system

La récupération de l'énergie des vibrations est un concept relativement nouveau qui peut être utilisé dans l'alimentation des dispositifs embarqués de puissance à micro-échelle avec l'énergie des vibrations omniprésentes dans l environnement. Cette thèse contribue à une étude générale des récupérateurs de l'énergie des vibrations (REV) employant des transducteurs électrostatiques. Un REV électrostatique typique se compose d'un transducteur capacitif, de l'électronique de conditionnement et d un élément de stockage. Ce travail se concentre sur l'examen du circuit de conditionnement auto-synchrone proposé en 2006 par le MIT, qui combine la pompe de charge à base de diodes et le convertisseur DC-DC inductif de type de flyback qui est entraîné par le commutateur. Cette architecture est très prometteuse car elle élimine la commande de grille précise des transistors utilisés dans les architectures synchrones, tandis qu'un commutateur unique se met en marche rarement. Cette thèse propose une analyse théorique du circuit de conditionnement. Nous avons développé un algorithme qui par commutation appropriée de flyback implémente la stratégie de conversion d'énergie optimale en tenant compte des pertes liées à la commutation. En ajoutant une fonction de calibration, le système devient adaptatif pour les fluctuations de l'environnement. Cette étude a été validée par la modélisation comportementale.Une autre contribution consiste en la réalisation de l'algorithme proposé au niveau du circuit CMOS. Les difficultés majeures de conception étaient liées à l'exigence de haute tension et à la priorité de la conception faible puissance. Nous avons conçu un contrôleur du commutateur haute tension de faible puissance en utilisant la technologie AMS035HV. Sa consommation varie entre quelques centaines de nanowatts et quelques microwatts, en fonction de nombreux facteurs - paramètres de vibrations externes, niveaux de tension de la pompe de charge, la fréquence de la commutation de commutateur, la fréquence de la fonction de calibration, etc.Nous avons également réalisé en silicium, fabriqué et testé un commutateur à haute tension avec une nouvelle architecture de l'élévateur de tension de faible puissance. En montant sur des composants discrets de la pompe de charge et du circuit de retour et en utilisant l'interrupteur conçu, nous avons caractérisé le fonctionnement large bande haute-tension du prototype de transducteur MEMS fabriqué à côté de cette thèse à l'ESIEE Paris. Lorsque le capteur est excité par des vibrations stochastiques ayant un niveau d'accélération de 0,8 g rms distribué dans la bande 110-170 Hz, jusqu'à 0,75 W de la puissance nette a été récupérée.Vibration energy harvesting is a relatively new concept that can be used in powering micro-scale power embedded devices with the energy of vibrations omnipresent in the surrounding. This thesis contributes to a general study of vibration energy harvesters (VEHs) employing electrostatic transducers. A typical electrostatic VEH consists of a capacitive transducer, conditioning electronics and a storage element. This work is focused on investigations of the reported by MIT in 2006 auto-synchronous conditioning circuit, which combines the diode-based charge pump and the inductive flyback energy return driven by the switch. This architecture is very promising since it eliminates precise gate control of transistors employed in synchronous architectures, while a unique switch turns on rarely. This thesis addresses the theoretical analysis of the conditioning circuit. We developed an algorithm that by proper switching of the flyback allows the optimal energy conversion strategy taking into account the losses associated with the switching. By adding the calibration function, the system became adaptive to the fluctuations in the environment. This study was validated by the behavioral modeling. Another contribution consists in realization of the proposed algorithm on the circuit level. The major design difficulties were related to the high-voltage requirement and the low-power design priority. We designed a high-voltage analog controller of the switch using AMS035HV technology. Its power consumption varies between several hundred nanowatts and a few microwatts, depending on numerous factors - parameters of external vibrations, voltage levels of the charge pump, frequency of the flyback switching, frequency of calibration function, etc. We also implemented on silicon, fabricated and tested a high-voltage switch with a novel low power level-shifting driver. By mounting on discrete components the charge pump and flyback circuit and employing the proposed switch, we characterized the wideband high-voltage operation of the MEMS transducer prototype fabricated alongside this thesis in ESIEE Paris. When excited with stochastic vibrations having an acceleration level of 0.8 g rms distributed in the band 110-170 Hz, up to 0.75 $\mu$W of net electrical power has been harvested.PARIS-JUSSIEU-Bib.électronique (751059901) / SudocSudocFranceF

Energy Efficiency in Communications and Networks

The topic of "Energy Efficiency in Communications and Networks" attracts growing attention due to economical and environmental reasons. The amount of power consumed by information and communication technologies (ICT) is rapidly increasing, as well as the energy bill of service providers. According to a number of studies, ICT alone is responsible for a percentage which varies from 2% to 10% of the world power consumption. Thus, driving rising cost and sustainability concerns about the energy footprint of the IT infrastructure. Energy-efficiency is an aspect that until recently was only considered for battery driven devices. Today we see energy-efficiency becoming a pervasive issue that will need to be considered in all technology areas from device technology to systems management. This book is seeking to provide a compilation of novel research contributions on hardware design, architectures, protocols and algorithms that will improve the energy efficiency of communication devices and networks and lead to a more energy proportional technology infrastructure

Resource-efficient algorithms and circuits for highly-scalable BMI channel architectures

The study of the human brain has for long fascinated mankind. This organ that controls all cognitive processes and physical actions remains, to this day, among the least understood biological systems. Several billions of neurons form intricate interconnected networks communicating information through through complex electrochemical activities. Electrode arrays, such as for EEG, ECoG, and MEAs (microelectrode arrays), have enabled the observation of neural activity through recording of these electrical signals for both investigative and clinical applications. Although MEAs are widely considered the most invasive such method for recording, they do however provide highest resolution (both spatially and temporally). Due to close proximity, each microelectrode can pick up spiking activity from multiple neurons. This thesis focuses on the design and implementation of novel circuits and systems suitable for high channel count implantable neural interfaces. Implantability poses stringent requirements on the design, such as ultra-low power, small silicon footprint, reduced communication bandwidth and high efficiency to avoid information loss. The information extraction chain typically involves signal amplification and conditioning, spike detection, and spike sorting to determine the spatial and time firing pattern of each neuron. This thesis first provides a background to the origin and basic electrophysiology of these biopotential signals followed by a thorough review of the relevant state-of-the circuits and systems for facilitating the neural interface. Within this context, novel front-end circuits are presented for achieving resource-constrained biopotential amplification whilst additionally considering the signal dynamics and realistic requirements for effective classification. Specifically, it is shown how a band-limited biopotential amplifier can reduce power requirements without compromising detectability. Furthermore through the development of a novel automatic gain control for neural spike recording, the dynamic range of the signal in subsequent processing blocks can be maintained in multichannel systems. This is particularly effective if now considering systems that no longer requiring independent tuning of amplification gains for each individual channel. This also alleviates the common requirement to over-spec the resolution in data conversion therefore saving power, area and data capacity. Dealing with basic spike detection and feature extraction, a novel circuit for maxima detection is presented for identifying and signalling the onset of spike peaks and troughs. This is then combined with a novel non-linear energy operator (NEO) preprocessor and applied to spike detection. This again contributes to the general theme of achieving a calibration-free multi-channel system that is signal-driven and adaptive. Another original contribution herein includes a spike rate encoder circuit suitable for applications that are not are not affected by providing multi-unit responses. Finally, spike sorting (feature extraction and clustering) is examined. A new method for feature extraction is proposed based on utilising the extrema of the first and second derivatives of the signal. It is shown that this provides an extremely resource-efficient metric than can achieve noise immunity than other methods of comparable complexity. Furthermore, a novel unsupervised clustering method is proposed which adaptively determines the number of clusters and assigns incoming spikes to appropriate cluster on-the-fly. In addition to high accuracy achieved by the combination of these methods for spike sorting, a major advantage is their low-computational complexity that renders them readily implementable in low-power hardware.Open Acces

Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D