Seventy Years of Getting Transistorized

Vacuum tubes appeared at the break of the twentieth century giving birth to electronics. By the 1930s, they had become established as a mature technology, spreading into areas such as radio communications, long distance radiotelegraphy, radio broadcasting, telephone communication and switching, sound recording and playing, television, radar, and air navigation. During World War II, vacuum tubes were used in the first electronic computers, which were built in the United Kingdom and the United States. Although vacuum tubes had been a successful technology, they were also bulky, fragile and expensive, had a short life, and consumed a lot of power to heat the thermo-emitters. These drawbacks promoted the search for completely new devices. Alternative solutions had long been considered, but without significant developments

High-frequency two-input CMOS OTA for continuous-time filter applications

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A high-frequency fully differential CMOS operational transconductance amplifier (OTA) is presented for continuous-time filter applications in the megahertz range. The proposed design technique combines a linear cross-coupled quad input stage with an enhanced folded-cascode circuit to increase the output resistance of the amplifier. SPICE simulations show that DC-gain enhancement can be obtained without significant bandwidth limitation. The two-input OTA developed is used in high-frequency tuneable filter design based on IFLF and LC ladder simulation structures. Simulated results of parameters and characteristics of the OTA and filters in a standard 1.2 μm CMOS process (MOSIS) are presented. A tuning circuit is also discussed.Peer reviewe

Conductance in Co/Al2O3/Si/Al2O3 permalloy with asymmetrically doped barrier

Permalloy magnetic tunnel junctions. Complementary low frequency noise measurements are used to understand the conductance results. The obtained data indicate the breakdown of the Coulomb blockade for thickness of the asymmetric silicon layer exceeding 1.2\AA . The crossover in the conductance, the dependence of the tunnelling magnetoresistance with the bias voltage and the noise below 80K correspond to 1 monolayer coverage. Interestingly, the zero bias magnetoresistance remains nearly unaffected by the presence of the silicon layer. The proposed model uses Larkin-Matveev approximation of tunnelling through a single impurity layer generalized to 3D and takes into account the variation of the barrier shape with the bias voltage. The main difference is the localization of all the impurity levels within a single atomic layer. In the high thickness case, up to 1.8\AA, we have introduced a phenomenological parameter, which reflects the number of single levels on the total density of silicon atoms.Comment: 10 pages, 13 figure

Correlation effects and spin dependent transport in carbon nanostructures

The impact of symmetry breaking perturbations on the spin dependent transport through carbon nanotube quantum dots in the Kondo regime is discussed.Comment: 10 pages, 6 figure

Why ferromagnetic semiconductors?

Rapid development of information technologies originates from the exponential increase in the density of information that can be processed, stored, and transfer by the unit area of relevant devices. There is, however, a growing amount of evidences that the progress achieved in this way approaches its limits. Various novel ideas put forward to circumvent barriers ahead are described. Particular attention is paid to those concepts which propose to exploit electron or nuclear spins as the information carriers. Here, ferromagnetic semiconductors of III-V or II-VI compounds containing a sizable concentration of transition metals appear as outstanding spintronic materials.Comment: 8 PDF pages, Polish Physical Soc. Meetin

Space station power semiconductor package

A package of high-power switching semiconductors for the space station have been designed and fabricated. The package includes a high-voltage (600 volts) high current (50 amps) NPN Fast Switching Power Transistor and a high-voltage (1200 volts), high-current (50 amps) Fast Recovery Diode. The package features an isolated collector for the transistors and an isolated anode for the diode. Beryllia is used as the isolation material resulting in a thermal resistance for both devices of .2 degrees per watt. Additional features include a hermetical seal for long life -- greater than 10 years in a space environment. Also, the package design resulted in a low electrical energy loss with the reduction of eddy currents, stray inductances, circuit inductance, and capacitance. The required package design and device parameters have been achieved. Test results for the transistor and diode utilizing the space station package is given

Development of deep submicron CMOS process for fabrication of high performance 0.25 nm transistors

An advanced process for fabrication of 0.25 μm CMOS transistors has been demonstrated. This process is designed for transistors with Lpoly = 0.25 μm and Leffective = 0.2 um on 150 mm (6”) silicon wafers. Devices with Leffective of 0.2 um and smaller have been tested and found operational. A 0.25 um NMOS transistor with drain current of 177 μA/μm at VG=VD=2.5 V and a PMOS transistor with drain current of 131 μA/μm at VG=VD=-2.5 V are reported. The threshold voltages are 1.0 V for the NMOS and -0.735 V for the PMOS transistors. These 0.25 um NMOS and PMOS are the smallest transistors ever fabricated at RIT. Many processes have been integrated to produce the final CMOS devices, including: 50 Å gate oxide with N2O, shallow trench isolation by chemical mechanical planarization (CMP), dual doped polysilicon gates for surface channel devices, ultra-shallow low doped source/drain extensions using low energy As and BF2 ions, rapid thermal dopant activation, Si3N4 sidewall spacers, TiSi2 salicide source/drain contacts and gates, uniformly doped twin wells, contact cut RIE and 2 level aluminum metallization