Efficient Modelling and Simulation Methodology for the Design of Heterogeneous Mixed-Signal Systems on Chip

Systems on Chip (SoCs) and Systems in Package (SiPs) are key parts of a continuously broadening range of products, from chip cards and mobile phones to cars. Besides an increasing amount of digital hardware and software for data processing and storage, they integrate more and more analogue/RF circuits, sensors, and actuators to interact with their (analogue) environment. This trend towards more complex and heterogeneous systems with more intertwined functionalities is made possible by the continuous advances in the manufacturing technologies and pushed by market demand for new products and product variants. Therefore, the reuse and retargeting of existing component designs becomes more and more important. However, all these factors make the design process increasingly complex and multidisciplinary. Nowadays, the design of the individual components is usually well understood and optimised through the usage of a diversity of CAD/EDA tools, design languages, and data formats. These are based on applying specific modelling/abstraction concepts, description formalisms (also called Models of Computation (MoCs)) and analysis/simulation methods. The designer has to bridge the gaps between tools and methodologies using manual conversion of models and proprietary tool couplings/integrations, which is error-prone and time-consuming. A common design methodology and platform to manage, exchange, and collaboratively develop models of different formats and of different levels of abstraction is missing. The verification of the overall system is a big problem, as it requires the availability of compatible models for each component at the right level of abstraction to achieve satisfying results with respect to the system functionality and test coverage, but at the same time acceptable simulation performance in terms of accuracy and speed. Thus, the big challenge is the parallel integration of these very different part design processes. Therefore, the designers need a common design and simulation platform to create and refine an executable specification of the overall system (a virtual prototype) on a high level of abstraction, which supports different MoCs. This makes possible the exploration of different architecture options, estimation of the performance, validation of re-used parts, verification of the interfaces between heterogeneous components and interoperability with other systems as well as the assessment of the impacts of the future working environment and the manufacturing technologies used to realise the system. For embedded Analogue and Mixed-Signal (AMS) systems, the C++-based SystemC with its AMS extensions, to which recent standardisation the author contributed, is currently establishing itself as such a platform. This thesis describes the author's contribution to solve the modelling and simulation challenges mentioned above in three thematic phases. In the first phase, the prototype of a web-based platform to collect models from different domains and levels of abstraction together with their associated structural and semantical meta information has been developed and is called ModelLib. This work included the implementation of a hierarchical access control mechanism, which is able to protect the Intellectual Property (IP) constituted by the model at different levels of detail. The use cases developed for this tool show how it can support the AMS SoC design process by fostering the reuse and collaborative development of models for tasks like architecture exploration, system validation, and creation of more and more elaborated models of the system. The experiences from the ModelLib development delivered insight into which aspects need to be especially addressed throughout the development of models to make them reusable: mainly flexibility, documentation, and validation. This was the starting point for the development of an efficient modelling methodology for the top-down design and bottom-up verification of RF Systems based on the systematic usage of behavioural models in the second phase. One outcome is the developed library of well documented, parameterisable, and pin-accurate VHDL-AMS models of typical analogue/digital/RF components of a transceiver. The models offer the designer two sets of parameters: one based on the performance specifications and one based on the device parameters back-annotated from the transistor-level implementation. The abstraction level used for the description of the respective analogue/digital/RF component behaviour has been chosen to achieve a good trade-off between accuracy, fidelity, and simulation performance. The pin-accurate model interfaces facilitate the integration of transistor-level models for the validation of the behavioural models or the verification of a component implementation in the system context. These properties make the models suitable for different design tasks such as architecture exploration or overall system validation. This is demonstrated on a model of a binary Frequency-Shift Keying (FSK) transmitter parameterised to meet very different target specifications. This project showed also the limits in terms of abstraction and simulation performance of the "classical" AMS Hardware Description Languages (HDLs). Therefore, the third and last phase was dedicated to further raise the abstraction level for the description of complex and heterogeneous AMS SoCs and thus enable their efficient simulation using different synchronised MoCs. This work uses the C++-based simulation framework SystemC with its AMS extensions. New modelling capabilities going beyond the standardised SystemC AMS extensions have been introduced to describe energy conserving multi-domain systems in a formal and consistent way at a high level of abstraction. To this end, all constants, variables, and parameters of the system model, which represent a physical quantity, can now declare their dimension and associated system of units as an intrinsic part of their data type. Assignments to them need to contain besides the value also the correct measurement unit. This allows a much more precise but still compact definition of the models' interfaces and equations. Thus, the C++ compiler can check the correct assembly of the components and the coherency of the equations by means of dimensional analysis. The implementation is based on the Boost.Units library, which employs template metaprogramming techniques. A dedicated filter for the measurement units data types has been implemented to simplify the compiler messages and thus facilitate the localisation of unit errors. To ensure the reusability of models despite precisely defined interfaces, their interfaces and behaviours need to be parametrisable in a well-defined manner. The enabling implementation techniques for this have been demonstrated with the developed library of generic block diagram component models for the Timed Data Flow (TDF) MoC of the SystemC AMS extensions. These techniques are also the key to integrate a new MoC based on the bond graph formalism into the SystemC AMS extensions. Bond graphs facilitate the unified description of the energy conserving parts of heterogeneous systems with the help of a small set of modelling primitives parametrisable to the physical domain. The resulting models have a simulation performance comparable to an equivalent signal flow model

Study, optimization and silicon implementation of a smart high-voltage conditioning circuit for electrostatic vibration energy harvesting system

La récupération de l'énergie des vibrations est un concept relativement nouveau qui peut être utilisé dans l'alimentation des dispositifs embarqués de puissance à micro-échelle avec l'énergie des vibrations omniprésentes dans l environnement. Cette thèse contribue à une étude générale des récupérateurs de l'énergie des vibrations (REV) employant des transducteurs électrostatiques. Un REV électrostatique typique se compose d'un transducteur capacitif, de l'électronique de conditionnement et d un élément de stockage. Ce travail se concentre sur l'examen du circuit de conditionnement auto-synchrone proposé en 2006 par le MIT, qui combine la pompe de charge à base de diodes et le convertisseur DC-DC inductif de type de flyback qui est entraîné par le commutateur. Cette architecture est très prometteuse car elle élimine la commande de grille précise des transistors utilisés dans les architectures synchrones, tandis qu'un commutateur unique se met en marche rarement. Cette thèse propose une analyse théorique du circuit de conditionnement. Nous avons développé un algorithme qui par commutation appropriée de flyback implémente la stratégie de conversion d'énergie optimale en tenant compte des pertes liées à la commutation. En ajoutant une fonction de calibration, le système devient adaptatif pour les fluctuations de l'environnement. Cette étude a été validée par la modélisation comportementale.Une autre contribution consiste en la réalisation de l'algorithme proposé au niveau du circuit CMOS. Les difficultés majeures de conception étaient liées à l'exigence de haute tension et à la priorité de la conception faible puissance. Nous avons conçu un contrôleur du commutateur haute tension de faible puissance en utilisant la technologie AMS035HV. Sa consommation varie entre quelques centaines de nanowatts et quelques microwatts, en fonction de nombreux facteurs - paramètres de vibrations externes, niveaux de tension de la pompe de charge, la fréquence de la commutation de commutateur, la fréquence de la fonction de calibration, etc.Nous avons également réalisé en silicium, fabriqué et testé un commutateur à haute tension avec une nouvelle architecture de l'élévateur de tension de faible puissance. En montant sur des composants discrets de la pompe de charge et du circuit de retour et en utilisant l'interrupteur conçu, nous avons caractérisé le fonctionnement large bande haute-tension du prototype de transducteur MEMS fabriqué à côté de cette thèse à l'ESIEE Paris. Lorsque le capteur est excité par des vibrations stochastiques ayant un niveau d'accélération de 0,8 g rms distribué dans la bande 110-170 Hz, jusqu'à 0,75 W de la puissance nette a été récupérée.Vibration energy harvesting is a relatively new concept that can be used in powering micro-scale power embedded devices with the energy of vibrations omnipresent in the surrounding. This thesis contributes to a general study of vibration energy harvesters (VEHs) employing electrostatic transducers. A typical electrostatic VEH consists of a capacitive transducer, conditioning electronics and a storage element. This work is focused on investigations of the reported by MIT in 2006 auto-synchronous conditioning circuit, which combines the diode-based charge pump and the inductive flyback energy return driven by the switch. This architecture is very promising since it eliminates precise gate control of transistors employed in synchronous architectures, while a unique switch turns on rarely. This thesis addresses the theoretical analysis of the conditioning circuit. We developed an algorithm that by proper switching of the flyback allows the optimal energy conversion strategy taking into account the losses associated with the switching. By adding the calibration function, the system became adaptive to the fluctuations in the environment. This study was validated by the behavioral modeling. Another contribution consists in realization of the proposed algorithm on the circuit level. The major design difficulties were related to the high-voltage requirement and the low-power design priority. We designed a high-voltage analog controller of the switch using AMS035HV technology. Its power consumption varies between several hundred nanowatts and a few microwatts, depending on numerous factors - parameters of external vibrations, voltage levels of the charge pump, frequency of the flyback switching, frequency of calibration function, etc. We also implemented on silicon, fabricated and tested a high-voltage switch with a novel low power level-shifting driver. By mounting on discrete components the charge pump and flyback circuit and employing the proposed switch, we characterized the wideband high-voltage operation of the MEMS transducer prototype fabricated alongside this thesis in ESIEE Paris. When excited with stochastic vibrations having an acceleration level of 0.8 g rms distributed in the band 110-170 Hz, up to 0.75 $\mu$W of net electrical power has been harvested.PARIS-JUSSIEU-Bib.électronique (751059901) / SudocSudocFranceF

System level performance and yield optimisation for analogue integrated circuits

Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield.This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype.For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse.A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology

UML-Based co-design framework for body sensor network applications

Ph.DDOCTOR OF PHILOSOPH

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Дослідження процесу збудження акустичних коливань перетворювачем ємнісного типу

Магістерська дисертація містить 98 сторінок, 42 рисунка, 25 таблиць, 35 джерел за переліком посилань. Робота направлена на вирішення проблеми проектування ультразвукових перетворювачів ємнісного типу для систем медичної діагностики. На основі аналізу світового досвіду виконана оцінка ефективності малогабаритних високочастотних перетворювачів при їх збудженні відносно низькими напругами. Проведено експериментальні дослідження для підтвердження фізичних процесів збудження коливань. Актуальність. П'єзоелектричні перетворювачі довгий час були домінуючою технологією в ультразвукових перетворювачах, але нещодавно з'явилися ємнісні мікромеханічні ультразвукові перетворювачі, що надають значні переваги, такі як широка смуга пропускання, легкість виготовлення великих масивів елементів та потенціал для інтеграції з існуючими електронними схемами. ЄМУП - це простий пристрій з двома пластинчасто-подібними електродами, зміщеними постійною напругою та збудженням додатковим змінним сигналом для гармонійного коливання однієї з пластин. ЄМУП забезпечують ряд переваг перед п'єзоелектричними перетворювачами: вони можуть бути виготовлені партіями з технологіями мікрообробки, що забезпечують жорсткі специфікації параметрів, чого важко досягнути у випадку із п'єзоелектриками, їх легше виготовити, ніж п'єзоелектричні перетворювачі. Технології серійного виробництва також дозволяють виготовляти матриці перетворювачів з різними робочими частотами на одній пластині та перетворювачі складної форми. Мета дослідження – покращення коефіцієнта електромеханічного зв’язку і механічних характеристик ємнісних перетворювачів шляхом підвищення напруги збудження коливань і аналіз отриманих результатів. Завдання дослідження. 1. Аналіз стану сучасних технологій збудження механічних коливань і фізичної суті процесу збудження коливань з використанням ємнісних ультразвукових перетворювачів. 2. Розробити конструкцію перетворювача і реалізувати її у вигляді прототипу. 3. Експериментально дослідити фізичний процес коливання, визначити оптимальні амплітуди збуджуючої напруги. 4. Розробити електричну схему для збудження коливань. 5. Дослідити можливі варіанти підвищення ефективності збудження коливань. Об’єкт дослідження – процес збудження ультразвукових коливань ємнісними мікромеханічними ультразвуковими перетворювачами. Предмет дослідження – метод збудження ультразвуку ємнісними перетворювачами і технічна реалізація цього процесу.The master's thesis contains 98 pages, 42 figures, 25 tables, 35 references. The work is aimed at solving the problem of designing capacitive-type ultrasonic transducers for medical diagnostics systems. Based on the analysis of world experience, the efficiency of small-size highfrequency converters for their excitation by relatively low voltages has been evaluated. Experimental studies have been conducted to confirm the physical processes of oscillation excitation. Piezoelectric transducers have long been the dominant technology in ultrasonic transducers, but capacitive micromechanical ultrasonic transducers have recently emerged that offer significant advantages such as wide bandwidth, ease of fabrication of large array elements and potential for integration and interoperability. EMUP is a simple device with two plate-like electrodes, offset by constant voltage and excitation by an additional variable signal for the harmonic oscillation of one of the plates. EMUs offer a number of advantages over piezoelectric converters: they can be manufactured in batches with micro-processing technologies that provide rigid parameter specifications, which are difficult to achieve in the case of piezoelectrics and are easier to manufacture than piezoelectric converters. The batch production technologies also allow the manufacture of arrays of converters with different operating frequencies on the same plate and converters of complex shape. The purpose of the study is to improve the electromechanical coupling coefficient and the mechanical characteristics of the capacitive converters by increasing the excitation voltage and analyzing the results obtained. Objectives of the study. 1. Analysis of the state of the art of technologies of excitation of mechanical vibrations and physical essence of the process of excitation of oscillations with the use of capacitive ultrasonic transducers. 2. Develop the design of the converter and implement it in the form of a prototype. 3. Experimentally investigate the physical process of oscillation, determine the optimal amplitudes of the exciting voltage. 4. Develop a circuit for excitation of oscillations. 5. Investigate possible ways to increase the efficiency of oscillation excitation. The object of study is the process of excitation of ultrasonic vibrations by capacitive micromechanical ultrasonic transducers. The subject of the study is the method of ultrasound excitation by capacitive transducers and the technical implementation of this process

Mixed-signal integrated circuits design and validation for automotive electronics applications

Automotive electronics is a fast growing market. In a field primarily dominated by mechanical or hydraulic systems, over the past few decades there has been exponential growth in the number of electronic components incorporated into automobiles. Partly thanks to the advance in high voltage smart power processes in nowadays cars is possible to integrate both power/high voltage electronics and analog/digital signal processing circuitry thus allowing to replace a lot of mechanical systems with electro-mechanical or fully electronic ones. High level modeling of complex electronic systems is gaining importance relatively to design space exploration, enabling shorter design and verification cycles, allowing reduced time-to-market. A high level model of a resistor string DAC to evaluate nonlinearities has been developed in MATLAB environment. As a test case for the model, a 10 bit resistive DAC in 0.18um is designed and the results were compared with the traditional transistor level approach. Then we face the analysis and design of a fundamental block: the bandgap voltage reference. Automotive requirements are tough, so the design of the voltage reference includes a pre-regulation part of the battery voltage that allows to enhance overall performances. Moreover an analog integrated driver for an automotive application whose architecture exploits today’s trends of analog-digital integration allowing a greater range of flexibility allowing high configurability and fast prototipization is presented. We covered also the mixed-signal verification approach. In fact, as complexity increases and mixed-signal systems become more and more pervasive, test and verification often tend to be the bottleneck in terms of time effort. A complete flow for mixed-signal verification using VHDL-AMS modeling and Python scripting is presented as an alternative to complex transistor level simulations. Finally conclusions are drawn