1,918 research outputs found
HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host
processor with programmable manycore accelerators (PMCAs) to combine
general-purpose computing with domain-specific, efficient processing
capabilities. While leading companies successfully advance their HESoC
products, research lags behind due to the challenges of building a prototyping
platform that unites an industry-standard host processor with an open research
PMCA architecture. In this work we introduce HERO, an FPGA-based research
platform that combines a PMCA composed of clusters of RISC-V cores, implemented
as soft cores on an FPGA fabric, with a hard ARM Cortex-A multicore host
processor. The PMCA architecture mapped on the FPGA is silicon-proven,
scalable, configurable, and fully modifiable. HERO includes a complete software
stack that consists of a heterogeneous cross-compilation toolchain with support
for OpenMP accelerator programming, a Linux driver, and runtime libraries for
both host and PMCA. HERO is designed to facilitate rapid exploration on all
software and hardware layers: run-time behavior can be accurately analyzed by
tracing events, and modifications can be validated through fully automated hard
ware and software builds and executed tests. We demonstrate the usefulness of
HERO by means of case studies from our research
DeSyRe: on-Demand System Reliability
The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints
From FPGA to ASIC: A RISC-V processor experience
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC
Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals
Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve
A low cost reconfigurable soft processor for multimedia applications: design synthesis and programming model
This paper presents an FPGA implementation of a low cost 8 bit reconfigurable processor core for media processing applications. The core is optimized to provide all basic arithmetic and logic functions required by the media processing and other domains, as well as to make it easily integrable into a 2D array. This paper presents an investigation of the feasibility of the core as a potential soft processing architecture for FPGA platforms. The core was synthesized on the entire Virtex FPGA family to evaluate its overall performance, scalability and portability. A special feature of the proposed architecture is its simple programming model which allows low level programming. Throughput results for popular benchmarks coded using the programming model and cycle accurate simulator are presented
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
IoT applications span a wide range in performance and memory footprint, under
tight cost and power constraints. High-end applications rely on power-hungry
Systems-on-Chip (SoCs) featuring powerful processors, large LPDDR/DDR3/4/5
memories, and supporting full-fledged Operating Systems (OS). On the contrary,
low-end applications typically rely on Ultra-Low-Power ucontrollers with a
"close to metal" software environment and simple micro-kernel-based runtimes.
Emerging applications and trends of IoT require the "best of both worlds":
cheap and low-power SoC systems with a well-known and agile software
environment based on full-fledged OS (e.g., Linux), coupled with extreme energy
efficiency and parallel digital signal processing capabilities. We present
HULK-V: an open-source Heterogeneous Linux-capable RISC-V-based SoC coupling a
64-bit RISC-V processor with an 8-core Programmable Multi-Core Accelerator
(PMCA), delivering up to 13.8 GOps, up to 157 GOps/W and accelerating the
execution of complex DSP and ML tasks by up to 112x over the host processor.
HULK-V leverages a lightweight, fully digital memory hierarchy based on
HyperRAM IoT DRAM that exposes up to 512 MB of DRAM memory to the host CPU.
Featuring HyperRAMs, HULK-V doubles the energy efficiency without significant
performance loss compared to featuring power-hungry LPDDR memories, requiring
expensive and large mixed-signal PHYs. HULK-V, implemented in Global Foundries
22nm FDX technology, is a fully digital ultra-low-cost SoC running a 64-bit
Linux software stack with OpenMP host-to-PMCA offload within a power envelope
of just 250 mW.Comment: This paper has been accepted as full paper at DATE23
https://www.date-conference.com/date-2023-accepted-papers#Regular-Paper
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