Weighted p-bits for FPGA implementation of probabilistic circuits

Probabilistic spin logic (PSL) is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve problems of optimization, inference and also to implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this paper we present a scalable FPGA implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped, and how invertibility can be applied to interesting problems such as the NP-complete Subset Sum Problem by solving a small instance of this problem in hardware

Towards Logic Functions as the Device using Spin Wave Functions Nanofabric

As CMOS technology scaling is fast approaching its fundamental limits, several new nano-electronic devices have been proposed as possible alternatives to MOSFETs. Research on emerging devices mainly focusses on improving the intrinsic characteristics of these single devices keeping the overall integration approach fairly conventional. However, due to high logic complexity and wiring requirements, the overall system-level power, performance and area do not scale proportional to that of individual devices. Thereby, we propose a fundamental shift in mindset, to make the devices themselves more functional than simple switches. Our goal in this thesis is to develop a new nanoscale fabric paradigm that enables realization of arbitrary logic functions (with high fan-in/fan-out) more efficiently. We leverage on non-equilibrium spin wave physical phenomenon and wave interference to realize these elementary functions called Spin Wave Functions (SPWFs). In the proposed fabric, computation is based on the principle of wave superposition. Information is encoded both in the phase and amplitude of spin waves; thereby providing an opportunity for compressed data representation. Moreover, spin wave propagation does not involve any physical movement of charge particles. This provides a fundamental advantage over conventional charge based electronics and opens new horizons for novel nano-scale architectures. We show several variants of the SPWFs based on topology, signal weights, control inputs and wave frequencies. SPWF based designs of arithmetic circuits like adders and parallel counters are presented. Our efforts towards developing new architectures using SPWFs places strong emphasis on integrated fabric-circuit exploration methodology. With different topologies and circuit styles we have explored how capabilities at individual fabric components level can affect design and vice versa. Our estimates on benefits vs. 45nm CMOS implementation show that, for a 1-bit adder, up to 40x reduction in area and 228x reduction in power is possible. For the 2-bit adder, results show that up to 33x area reduction and 222x reduction in power may be possible. Building large scale SPWF-based systems, requires mechanisms for synchronization and data streaming. In this thesis, we present data streaming approaches based on Asynchronous SPWFs (A-SPWFs). As an example, a 32-bit Carry Completion Sensing Adder (CCSA) is shown based on the A-SPWF approach with preliminary power, performance and area evaluations

Hardware emulation of stochastic p-bits for invertible logic

The common feature of nearly all logic and memory devices is that they make use of stable units to represent 0's and 1's. A completely different paradigm is based on three-terminal stochastic units which could be called "p-bits", where the output is a random telegraphic signal continuously fluctuating between 0 and 1 with a tunable mean. p-bits can be interconnected to receive weighted contributions from others in a network, and these weighted contributions can be chosen to not only solve problems of optimization and inference but also to implement precise Boolean functions in an inverted mode. This inverted operation of Boolean gates is particularly striking: They provide inputs consistent to a given output along with unique outputs to a given set of inputs. The existing demonstrations of accurate invertible logic are intriguing, but will these striking properties observed in computer simulations carry over to hardware implementations? This paper uses individual micro controllers to emulate p-bits, and we present results for a 4-bit ripple carry adder with 48 p-bits and a 4-bit multiplier with 46 p-bits working in inverted mode as a factorizer. Our results constitute a first step towards implementing p-bits with nano devices, like stochastic Magnetic Tunnel Junctions

A Novel Reconfiguration Scheme in Quantum-Dot Cellular Automata for Energy Efficient Nanocomputing

Quantum-Dot Cellular Automata (QCA) is currently being investigated as an alternative to CMOS technology. There has been extensive study on a wide range of circuits from simple logical circuits such as adders to complex circuits such as 4-bit processors. At the same time, little if any work has been done in considering the possibility of reconfiguration to reduce power in QCA devices. This work presents one of the first such efforts when considering reconfigurable QCA architectures which are expected to be both robust and power efficient. We present a new reconfiguration scheme which is highly robust and is expected to dissipate less power with respect to conventional designs. An adder design based on the reconfiguration scheme will be presented in this thesis, with a detailed power analysis and comparison with existing designs. In order to overcome the problems of routing which comes with reconfigurability, a new wire crossing mechanism is also presented as part of this thesis