63 research outputs found

    Ultra-low power circuits using graphene p-n junctions and adiabatic computing

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    Recent works have proven the functionality of electrostatically controlled graphene p–n junctions that can serve as basic primitive for the implementation of a new class of compact graphene-based reconfigurable multiplexer logic gates. Those gates, referred as RG-MUXes, while having higher expressive power and better performance w.r.t. standard CMOS gates, they also have the drawback of being intrinsically less power/energy efficient. In this work we address this problem from a circuit perspective, namely, we revisit RG-MUXes as devices that can operate adiabatically and hence with ultra-low (ideally, almost zero) power consumption. More specifically, we show how to build basic logic gates and, eventually, more complex logic functions, by appropriately interconnecting graphene-based p–n junctions as to implement the adiabatic charging principle. We provide a comparison in terms of power and performance against both adiabatic CMOS and their non-adiabatic graphene-based counterparts; characterization results collected from SPICE simulations on a set of representative functions show that the proposed ultra-low power graphene circuits can operate with 1.5–4 orders of magnitude less average power w.r.t. adiabatic CMOS and non-adiabatic graphene counterparts respectively. When it comes to performance, adiabatic graphene shows 1.3 (w.r.t. adiabatic CMOS) to 4.5 orders of magnitude (w.r.t. non-adiabatic technologies) better power-delay product

    Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization

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    As an answer to the new electronics market demands, semiconductor industry is looking for different materials, new process technologies and alternative design solutions that can support Silicon replacement in the VLSI domain. The recent introduction of graphene, together with the option of electrostatically controlling its doping profile, has shown a possible way to implement fast and power efficient Reconfigurable Gates (RGs). Also, and this is the most important feature considered in this work, those graphene RGs show higher expressive power, i.e., they implement more complex functions, like Majority, MUX, XOR, with less area w.r.t. CMOS counterparts. Unfortunately, state-of-the-art synthesis tools, which have been customized for standard NAND/NOR CMOS gates, do not exploit the aforementioned feature of graphene RGs. In this paper, we present a post-synthesis tool that translates the gate level netlist obtained from commercial synthesis tools to a more optimized netlist that can efficiently integrate graphene RGs. Results conducted on a set of open-source benchmarks demonstrate that the proposed strategy improves, on average, both area and performance by 17% and 8.17% respectively

    CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems

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    As an answer to More Moore paradigm, Complementary Metal Oxide Semiconductor (CMOS) technology is continuously scaled to nanometer lengths and the silicon channel has reached its physical limit. It is time for the industry to explore novel material based devices that support future integrated circuits. Graphene is a two dimensional material which can be patterned through existing lithography process, therefore representing the most interesting material for concurrent, single-layer integration of devices and interconnects. Moreover, it shows unique mechanical properties alowing for the growth of new smart devices (e.g. wearable computing). In this dissertation, we focus on a novel device called as multi function reconfigurable gate proposed by IBM. This device consists of coplanar split gates underneath a large graphene sheet. A thin dielectric oxide layer separates the gates and the graphene sheet. Three metal-graphene contacts are present on top of the graphene sheet, called as front metal-graphene contacts. The co-planar gates dope the graphene electrostatically by using bipolar voltages. Here, we define logic ‘0’ as negative voltage (-Vdd/2) and logic ‘1’ (+Vdd/2) as positive voltage. The gates are connected to ‘0’ and ‘1’ making the graphene region above the gates p-type and n-type, respectively. The device do not rely on patterning the graphene sheet into nanoribbons. Advanced CMOS lithography techniques can be efficiently used for the gate patterning to achieve high density integration. Thus, this device is feasible for manufacturing and does not introduce any edge effects on the carriers. Using the above mentioned multi function reconfigurable gate, with appropriate terminal connections, a graphene 2:1 multiplexer is realized. An equivalent electrical model (also verilog-A model) is developed which is integrated with commercial SPICE simulators. With appropriate signals at the data inputs of the graphene 2:1 multiplexer, several other basic boolean logic gates (Inv, AND, OR etc) are realized. Some of these gates (like AND etc) have multiple architectures and a thorough comparison in terms of power and performance is presented. For the graphene reconfigurable gate based logic gates, we identify the possible timing arcs. The timing arc is defined from the input node to the output node. Only those input node which is responsible for a signal transition at the output terminal are considered. Two classes of timing arcs are identified, one from back gate terminals to output terminal termed as back-to-out transition, second from front contact terminal to the output terminal termed as front-to-out transition. An analytical model for delay and power for each of these timing arcs are presented and validated through SPICE simulator. The model validation is done for a range of input transition time and output load capacitance. The next step is to build integrated circuits with these graphene based gates. This is termed as synthesis and is present in the initial stage of the traditional IC design flow. There are various synthesis methods for designing conventional CMOS based circuits. These methods (namely Standard Cell Mapping (STC), Binary Decision Diagrams (BDD) and Look Up Table (LUT)) can be adopted for graphene RG based gates too. Various benchmark circuits implemented with these methods are characterized for power, area and performance. This helps designers in identifying the best implementation style for low power and high performance circuit. From testability perspective, the effect of various physical defects such as Short circuit between device terminals and open terminals on the graphene RG based logic gates is presented in this thesis. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, have been analyzed and mapped at a higher level of abstraction using proper fault models. Finally, in this thesis we propose ultra low power graphene logic gates, based on Adiabatic Computing. We design graphene pn-junction based adiabatic logic gates (INV/AND/OR) and are characterized for power and performance. A comparison between the graphene pn-junction based adiabatic logic gates and non adiabatic graphene logic gates is drawn and the adiabatic gates proved to have significant power savings

    Use of Mycobacterium smegmatis Deficient in ADP-Ribosyltransferase as Surrogate for Mycobacterium tuberculosis in Drug Testing and Mutation Analysis

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    Rifampicin (Rif) is a first line drug used for tuberculosis treatment. However, the emergence of drug resistant strains has necessitated synthesis and testing of newer analogs of Rif. Mycobacterium smegmatis is often used as a surrogate for M. tuberculosis. However, the presence of an ADP ribosyltransferase (Arr) in M. smegmatis inactivates Rif, rendering it impractical for screening of Rif analogs or other compounds when used in conjunction with them (Rif/Rif analogs). Rifampicin is also used in studying the role of various DNA repair enzymes by analyzing mutations in RpoB (a subunit of RNA polymerase) causing Rif resistance. These analyses use high concentrations of Rif when M. smegmatis is used as model. Here, we have generated M. smegmatis strains by deleting arr (Delta arr). The M. smegmatis Delta arr strains show minimum inhibitory concentration (MIC) for Rif which is similar to that for M. tuberculosis. The MICs for isoniazid, pyrazinamide, ethambutol, ciprofloxacin and streptomycin were essentially unaltered for M. smegmatis Delta arr. The growth profiles and mutation spectrum of Delta arr and, Delta arr combined with Delta udgB (udgB encodes a DNA repair enzyme that excises uracil) strains were similar to their counterparts wild-type for arr. However, the mutation spectrum of Delta fpg Delta arr strain differed somewhat from that of the Delta fpg strain (fpg encodes a DNA repair enzyme that excises 8-oxo-G). Our studies suggest M. smegmatis Delta arr strain as an ideal model system in drug testing and mutation spectrum determination in DNA repair studies

    Effect of acidified NaNO<sub>2</sub> on growth.

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    <p><i>M</i>. <i>smegmatis</i> (<i>Msm</i>) strains were grown in 7H9 to saturation at 37°C and diluted 100 fold in 7H9 (pH 5.5) either in the absence (0 mM) or presence of (0.5 mM, 1 mM, or 1.5 mM) NaNO<sub>2</sub>. The growth was monitored as OD at 600 nm in Bioscreen kinetic growth reader at intervals of 3 h for 40 h. The growth was plotted using GraphPad prism 5 software.</p

    Schottky‐barrier graphene nanoribbon field‐effect transistors‐based field‐programmable gate array's configurable logic block and routing switch

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    Configurable electronic devices have been developed to provide more flexibility in the advanced digital system design, which needs more device density and there by relies on device scaling. Besides, International Technology Roadmap for Semiconductor (ITRS) has predicted scaling limitation for conventional silicon (Si)‐based devices. Researches on post‐Si materials have proved that carbon could be one of the material which can replaced with Si. Owing to exceptional properties of graphene, designs with graphene‐based devices can replace with Si based ones. This study proposes design and characterisation of graphene‐based simple field‐programmable gate array as a platform of configurable logic structure for future developments. This study focuses on design and characterisation of configurable logic block (CLB), flip‐flop as internal sequential logic devices in CLB, and routing switch, which are designed using graphene nanoribbon field‐effect transistor (GNRFET). The results indicate that proposed CLB is much faster than Si based one and power–delay product of proposed sequential element is much lesser than its counterpart in Si‐based technology. In addition, the proposed GNRFET‐based routing switch requires minimum count of 6 transistors to provide desirable functionality. Foreseeing the feasibility of architecture, this study suggests the possible layout of the proposed logic elements needed for CLB

    Physiological role of FolD (methylenetetrahydrofolate dehydrogenase), FchA (methenyltetrahydrofolate cyclohydrolase) and Fhs (formyltetrahydrofolate synthetase) from Clostridium perfringens in a heterologous model of Escherichia coli

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    Most organisms possess bifunctional FolD 5,10-methylenetetrahydrofolate (5,10-CH2-THF) dehydrogenase-cyclohydrolase] to generate NADPH and 10-formyltetrandrofolate (10-CHO-THF) required in various metabolic steps. In addition, some organisms including Clostridium perfringens possess another protein, Fhs (formyltetrahydrofolate synthetase), to synthesize 10-CHO-THF. Here, we show that unlike the bifunctional FolD of Escherichia coli (Eco FolD), and contrary to its annotated bifunctional nature, C. perfringens FolD (Cpe FoID) is a monofunctional 5,10-CH2-THF dehydrogenase. The dehydrogenase activity of Cpe FoID is about five times more efficient than that of Eco FolD. The 5,10-methenyltetrahydrofolate (5,10-CH+-THF) cyclohydrolase activity in C. perfringens is provided by another protein, FchA (5,10-CH+-THF cyclohydrolase), whose cyclohydrolase activity is similar to 10 times more efficient than that of Eco FolD. Kinetic parameters for Cpe Fhs were also determined for utilization of all of its substrates. Both Cpe FoID and Cpe FchA are required to substitute for the single bifunctional FolD in E. coli. The simultaneous presence of Cpe FoID and Cpe FchA is also necessary to rescue an E coli folD deletion strain (harbouring Cpe Fhs support) for its formate and glycine auxotrophies, and to alleviate its susceptibility to trimethoprim (an antifolate drug) or UV light. The presence of the three clostridial proteins (FolD, FchA and Fhs) is required to maintain folate homeostasis in the cell
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