An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating

© 2015 IEEE.Leakage power is an important component of the total power consumption in field-programmable gate arrays (FPGAs) built using 90-nm and smaller technology nodes. Power gating was shown to be effective at reducing the leakage power. Previous techniques focus on turning OFF unused FPGA resources at configuration time; the benefit of this approach depends on resource utilization. In this paper, we present an FPGA architecture that enables dynamically controlled power gating, in which FPGA resources can be selectively powered down at run-time. This could lead to significant overall energy savings for applications having modules with long idle times. We also present a CAD flow that can be used to map applications to the proposed architecture. We study the area and power tradeoffs by varying the different FPGA architecture parameters and power gating granularity. The proposed CAD flow is used to map a set of benchmark circuits that have multiple power-gated modules to the proposed architecture. Power savings of up to 83% are achievable for these circuits. Finally, we study a control system of a robot that is used in endoscopy. Using the proposed architecture combined with clock gating results in up to 19% energy savings in this application

High quality testing of grid style power gating

This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test qualit

Data-Width-Driven Power Gating of Integer Arithmetic Circuits

When performing narrow-width computations, power gating of unused arithmetic circuit portions can significantly reduce leakage power. We deploy coarse-grain power gating in 32-bit integer arithmetic circuits that frequently will operate on narrow-width data. Our contributions include a design framework that automatically implements coarse-grain power-gated arithmetic circuits considering a narrow-width input data mode, and an analysis of the impact of circuit architecture on the efficiency of this data-width-driven power gating scheme. As an example, with a performance penalty of 6.7%, coarse-grain power gating of a 45-nm 32-bit multiplier is demonstrated to yield an 11.6x static leakage energy reduction per 8x8-bit operation

Design and Analysis of Low Power Dual Edge Triggered Mechanism Flip-Flop Employing Power Gating Methodology

The advancement of battery operated designs has abundantly increases the memory elements and registers to be operated in ultra-low power. That is the this paper we have proposed a design of CT_C DET flip-flop with power gating technique which is the most efficient power consuming reduction technique.  The design of the power gating technique involves the pull-up transistor in the Vdd of the circuit and pull-down transistor in the ground terminal. This power gating technique reduces the power consumption by more than 40% than that of the existing design

Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology

LOW POWER ASIC IMPLEMENTATION OF A 256 BIT KEY AES CRYPTO-PROCESSOR AT 45NM TECHNOLOGY

Advanced Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. Low power devices have gained extreme importance in market today. Power dissipation is one of the most important design constraints to be handled well. A key to successful power management is automatic power reduction. This enables designers to meet their power budgets without adversely affecting their productivity or time to market. In this paper power gating techniques applied on AES crypto-processor is depicted. The goal of power gating is to minimize leakage power by temporarily cutting power off to selective blocks that are not required in the current operation. This AES design was implemented using Verilog HDL and synthesized with Synopsys DC Compiler using Nangate 45 nm open cell library, physical design implementation and power gating was performed using SOC Encounter and achieved a power reduction up to 40%

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

The Network-on-Chip (NoC) router buffers play an instrumental role in the performance of both the interconnection fabric and the entire multi-/many-core system. Nevertheless, the buffers also constitute the major leakage power consumers in NoC implementations. Traditionally, they are designed to accommodate worst-case traffic scenarios, so they tend to remain idle, or under-utilized, for extended periods of time. The under-utilization of these valuable resources is exemplified when one profiles real application workloads; the generated traffic is bursty in nature, whereby high traffic periods are sporadic and infrequent, in general. The mitigation of the leakage power consumption of NoC buffers via power gating has been explored in the literature, both at coarse (router-level) and fine (buffer-level) granularities. However, power gating at the router granularity is suitable only for low and medium traffic conditions, where the routers have enough opportunities to be powered down. Under high traffic, the sleeping potential rapidly diminishes. Moreover, disabling an entire router greatly affects the NoC functionality and the network connectivity. This article presents BlackOut, a fine-grained power-gating methodology targeting individual router buffers. The goal is to minimize leakage power consumption, without adversely impacting the system performance. The proposed framework is agnostic of the routing algorithm and the network topology, and it is applicable to any router micro-architecture. Evaluation results obtained using both synthetic traffic patterns and real applications in 64-core systems indicate energy savings of up to 70%, as compared to a baseline NoC, with a near-negligible performance overhead of around 2%. BlackOut is also shown to significantly outperformby 35%, on averagetwo current state-of-the-art power-gating solutions, in terms of energy savings. Not tailored to any topology, routing algorithm and NoC router architecture.Router-to-router communication. No need for custom, region-based/global networks.Effective at low, medium and high traffic. Other solutions are more restrictive.+35% energy saving, on average, against two state-of-the-art power-gating solutions.Negligible performance overhead (+2%) compared to the baseline architecture