Advanced Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. Low power devices have gained extreme importance in market today. Power dissipation is one of the most important design constraints to be handled well. A key to successful power management is automatic power reduction. This enables designers to meet their power budgets without adversely affecting their productivity or time to market. In this paper power gating techniques applied on AES crypto-processor is depicted. The goal of power gating is to minimize leakage power by temporarily cutting power off to selective blocks that are not required in the current operation. This AES design was implemented using Verilog HDL and synthesized with Synopsys DC Compiler using Nangate 45 nm open cell library, physical design implementation and power gating was performed using SOC Encounter and achieved a power reduction up to 40%
