The 40 Gbps cascaded bit-interleaving PON

A

Voltage controlled oscillators for 40Gbit/s cascaded bit-interleaving PON

Technologies such as the Internet-of-Things and cloud services demand dynamic bandwidth allocation flexibility, which is not offered by the currently deployed solutions. The Bit-Interleaving PON (BiPON) and its cascaded extension the Cascaded Bit-Interleaving PON (CBI-PON) offer a solution that allows to increase bandwidths, reduce power consumption and have a much more flexible dynamic bandwidth allocation scheme. CBI-PON consists of multiple levels of BiPON with different line rates. For each of these line rates, clock-and-data recovery must be performed, which requires a set of different Voltage Controlled Oscillators (VCOs). This paper presents the VCOs designed for the CABINET chip, an implementation of a CBI-PON network device, allowing clock-and-data recovery for 40Gbit/s, 10 Gbit/s and 2.5 Gbit/s line rates

10 Gbit/s bit interleaving CDR for low-power PON

A novel, low power, downstream clock and data recovery (CDR)- decimator architecture is proposed for next generation, energy efficient 10 Gbit/s optical network units (ONUs). The architecture employs a new time division multiplexing bit-interleaving downstream concept for passive optical networks (Bi-PON) allowing early decimation of the incoming data and lowering of the processing speed to the user rate of the ONU, thus reducing the power consumption significantly

CBI: a scalable energy-efficient protocol for metro/access networks

This paper presents a scalable energy-efficient MAC/PHY protocol for building a metro/access network. The proposed cascaded bit-interleaving (CBI) protocol extends the previously reported bit-interleaving concept to a multi-level paradigm. Moreover, a 40Gb/s 3-level electrical duobinary based physical layer scheme has been proposed for cost and energy saving, especially for end terminals. We compared two implementation approaches in terms of optical budget and transmission penalties. The initial estimate from the proof-ofconcept full-custom ASIC design shows that an ultra-low power metro/access network can be realized

Energy-efficiency improvements for optical access

This article discusses novel approaches to improve energy efficiency of different optical access technologies, including time division multiplexing passive optical network (TDM-PON), time and wavelength division multiplexing PON (TWDM-PON), point-to-point (PTP) access network, wavelength division multiplexing PON (WDM-PON), and orthogonal frequency division multiple access PON (OFDMA-PON). These approaches include cyclic sleep mode, energy-efficient bit interleaving protocol, power reduction at component level, or frequency band selection. Depending on the target optical access technology, one or a combination of different approaches can be applied

A low power 40 Gbit/s cascaded extension to bit-interleaving optical networks enabling next-generation metro/access connectivity

C

A low-energy rate-adaptive bit-interleaved passive optical network

Energy consumption of customer premises equipment (CPE) has become a serious issue in the new generations of time-division multiplexing passive optical networks, which operate at 10 Gb/s or higher. It is becoming a major factor in global network energy consumption, and it poses problems during emergencies when CPE is battery-operated. In this paper, a low-energy passive optical network (PON) that uses a novel bit-interleaving downstream protocol is proposed. The details about the network architecture, protocol, and the key enabling implementation aspects, including dynamic traffic interleaving, rate-adaptive descrambling of decimated traffic, and the design and implementation of a downsampling clock and data recovery circuit, are described. The proposed concept is shown to reduce the energy consumption for protocol processing by a factor of 30. A detailed analysis of the energy consumption in the CPE shows that the interleaving protocol reduces the total energy consumption of the CPE significantly in comparison to the standard 10 Gb/s PON CPE. Experimental results obtained from measurements on the implemented CPE prototype confirm that the CPE consumes significantly less energy than the standard 10 Gb/s PON CPE

Evaluating application vulnerability to soft errors in multi-level cache hierarchy

As the capacity of cache increases dramatically with new processors, soft errors originating in cache has become a major reliability concern for high performance processors. This paper presents application specific soft error vulnerability analysis in order to understand an application's responses to soft errors from different levels of caches. Based on a high-performance processor simulator called Graphite, we have implemented a fault injection framework that can selectively inject bit flips to different levels of caches. We simulated a wide range of relevant bit error patterns and measured the applications' vulnerabilities to bit errors. Our experimental results have shown the various vulnerabilities of applications to bit errors from different levels of caches; the results have also indicated the probabilities of different behaviors from the applications