Palladium gates for reproducible quantum dots in silicon

We replace the established aluminium gates for the formation of quantum dots in silicon with gates made from palladium. We study the morphology of both aluminium and palladium gates with transmission electron microscopy. The native aluminium oxide is found to be formed all around the aluminium gates, which could lead to the formation of unintentional dots. Therefore, we report on a novel fabrication route that replaces aluminium and its native oxide by palladium with atomic-layer-deposition-grown aluminium oxide. Using this approach, we show the formation of low-disorder gate-defined quantum dots, which are reproducibly fabricated. Furthermore, palladium enables us to further shrink the gate design, allowing us to perform electron transport measurements in the few-electron regime in devices comprising only two gate layers, a major technological advancement. It remains to be seen, whether the introduction of palladium gates can improve the excellent results on electron and nuclear spin qubits defined with an aluminium gate stack

Anisotropic Pauli spin blockade in hole quantum dots

We present measurements on gate-defined double quantum dots in Ge-Si core-shell nanowires, which we tune to a regime with visible shell filling in both dots. We observe a Pauli spin blockade and can assign the measured leakage current at low magnetic fields to spin-flip cotunneling, for which we measure a strong anisotropy related to an anisotropic g-factor. At higher magnetic fields we see signatures for leakage current caused by spin-orbit coupling between (1,1)-singlet and (2,0)-triplet states. Taking into account these anisotropic spin-flip mechanisms, we can choose the magnetic field direction with the longest spin lifetime for improved spin-orbit qubits

Depletion-mode Quantum Dots in Intrinsic Silicon

We report the fabrication and electrical characterization of depletion-mode quantum dots in a two-dimensional hole gas (2DHG) in intrinsic silicon. We use fixed charge in a SiO$_2$/Al$_2$O$_3$ dielectric stack to induce a 2DHG at the Si/SiO$_2$ interface. Fabrication of the gate structures is accomplished with a single layer metallization process. Transport spectroscopy reveals regular Coulomb oscillations with charging energies of 10-15 meV and 3-5 meV for the few- and many-hole regimes, respectively. This depletion-mode design avoids complex multilayer architectures requiring precision alignment, and allows to adopt directly best practices already developed for depletion dots in other material systems. We also demonstrate a method to deactivate fixed charge in the SiO$_2$/Al$_2$O$_3$ dielectric stack using deep ultraviolet light, which may become an important procedure to avoid unwanted 2DHG build-up in Si MOS quantum bits.Comment: Accepted to Applied Physics Letters. 5 pages, 3 figure

A fabrication guide for planar silicon quantum dot heterostructures

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.Comment: Accepted for publication in Nanotechnology. 31 pages, 12 figure

Hard superconducting gap and diffusion-induced superconductors in Ge-Si nanowires

We show a hard induced superconducting gap in a Ge-Si nanowire Josephson transistor up to in-plane magnetic fields of $250$ mT, an important step towards creating and detecting Majorana zero modes in this system. A hard induced gap requires a highly homogeneous tunneling heterointerface between the superconducting contacts and the semiconducting nanowire. This is realized by annealing devices at $180$ $^\circ$C during which aluminium inter-diffuses and replaces the germanium in a section of the nanowire. Next to Al, we find a superconductor with lower critical temperature ($T_\mathrm{C}=0.9$ K) and a higher critical field ($B_\mathrm{C}=0.9-1.2$ T). We can therefore selectively switch either superconductor to the normal state by tuning the temperature and the magnetic field and observe that the additional superconductor induces a proximity supercurrent in the semiconducting part of the nanowire even when the Al is in the normal state. In another device where the diffusion of Al rendered the nanowire completely metallic, a superconductor with a much higher critical temperature ($T_\mathrm{C}=2.9$ K) and critical field ($B_\mathrm{C}=3.4$ T) is found. The small size of diffusion-induced superconductors inside nanowires may be of special interest for applications requiring high magnetic fields in arbitrary direction