On the benefit of modifying the strategic allocation of cyclically calling vessels for multi-terminal container operators

We present a case study based on a multi-terminal container operation in Antwerp, Belgium, where a set of cyclically calling container vessels is processed. The operator faces the problem of strategically allocating a terminal, a berthing interval, and a variable number of quay cranes to the vessels in the set. Restricting properties are terminal quay lengths, number of quay cranes and storage capacities. Currently, the operator's objective is to satisfy the preferences of the vessel lines, with respect to a terminal and berthing time, as much as possible. We are interested in the benefit of modifying a given allocation, i.e. the potential crane and inter-terminal costs savings if specific changes to a given allocation are allowed. An MILP is implemented in a two-step optimization, which enables us to efficiently investigate the benefit of modification. Experimental results suggest that small changes in a given allocation may lead to significant cost savings

Robust cyclic berth planning of container vessels

We consider a container terminal operator who faces the problem of constructing a cyclic berth plan. Such a plan defines the arrival and departure times of each cyclically calling vessel on a terminal, taking into account the expected number of containers to be handled and the necessary quay and crane capacity to do so. Conventional berth planning methods ignore the fact that, in practice, container terminal operator and shipping line agree upon an arrival window rather than an arrival time: if a vessel arrives within that window then a certain vessel productivity and hence departure time is guaranteed. The contributions of this paper are twofold. We not only minimize the peak loading of quay cranes in a port, but also explicitly take into account the arrival window agreements between the terminal operator and shipping lines. We present a robust optimization model for cyclic berth planning. Computational results on a real-world scenario for a container terminal in Antwerp show that the robust planning model can reach a substantial reduction in the crane capacity that is necessary to meet the window arrival agreements, as compared to a deterministic planning approach

A formal model for defining and classifying delay-insensitive circuits and systems

Jan Tijmen Udding received the B.S. and M.S. degrees in mathematics, and the Ph.D. degree in computer science from the Eindhoven University of Technology, Eindhoven, The Netherlands, in 1975, 1980, and 1984, respectively. Currently he is an Assistant Professor with the Department of Computer Science at Washington University, St. Louis, Missouri, and an Associate Professor with the Department of Computer Science at the Eindhoven University of Technology. His research interests are mathematical aspects of VLSI, concurrency, program derivation and correctness, and functional programming

A termination and time complexity argument

Termination of an algorithm is usually obvious. In a few cases, however, it is a challenge to find a correct termination argument. In this note we give an example of such a problem and provide not only an argument for termination but also for the time complexity of the algorithm

Building finite automata from DI specifications

Numerous formalisms exist to specify delay-insensitive computations and their implementations. It is not always straightforward to compare specifications in the different formalisms. One way of comparing specifications is transforming them to automata in which nodes are annotated with progress requirement. In this paper we present an alogorithm that transforms DI-algebra recursive process expressions into finite automata. In doing so we develop an operational semantics for DI-algebra. The algorithm has been proven correct, and we highlight the most interesting aspects of that proof. The algorithm has been implemented and turns out to be very valuable in the process of getting a specification right