Improved Photoresist Coating for Making CNT Field Emitters

An improved photoresist-coating technique has been developed for use in the fabrication of carbon-nanotube- (CNT) based field emitters is described. The improved photoresist coating technique overcomes what, heretofore, has been a major difficulty in the fabrication process

Four-Point-Latching Microactuator

An experimental inchworm-type linear microactuator is depicted. This microactuator is a successor to one described in "MEMS-Based Piezoelectric/Electrostatic Inchworm Actuator" (NPO-30672), NASA Tech Briefs, Vol. 27, No. 6 (June 2003), page 68. Both actuators are based on the principle of using a piezoelectric transducer operated in alternation with electrostatically actuated clutches to cause a slider to move in small increments. However, the design of the present actuator incorporates several improvements over that of the previous one. The most readily apparent improvement is in geometry and, consequently, in fabrication: In the previous actuator, the inchworm motion was perpendicular to the broad faces of a flat silicon wafer on which the actuator was fabricated, and fabrication involved complex processes to form complex three-dimensional shapes in and on the wafer. In the present actuator, the inchworm motion is parallel to the broad faces of a wafer on which it is fabricated. The components needed to produce the in-plane motion are nearly planar in character and, consequently, easier to fabricate. Other advantages of the present design are described, including that the previous actuator contained two clutches (denoted 'holders' in the cited prior article), the present actuator contains four clutches. The operational sequence of the previous two-clutch actuator is similar. However, the two-clutch configuration is susceptible to tilt of the slider and a consequent large increase in drag. Hence, the primary operational advantages of the present four-point-latching design over the prior two-point-latching design are less drag and greater control robustness arising from greater stability of the orientation of the slider

Systems and Methods for Implementing Robust Carbon Nanotube-Based Field Emitters

Systems and methods in accordance with embodiments of the invention implement carbon nanotube-based field emitters. In one embodiment, a method of fabricating a carbon nanotube field emitter includes: patterning a substrate with a catalyst, where the substrate has thereon disposed a diffusion barrier layer; growing a plurality of carbon nanotubes on at least a portion of the patterned catalyst; and heating the substrate to an extent where it begins to soften such that at least a portion of at least one carbon nanotube becomes enveloped by the softened substrate

Fabrication of Gate-Electrode Integrated Carbon-Nanotube Bundle Field Emitters

A continuing effort to develop carbon-nanotube-based field emitters (cold cathodes) as high-current-density electron sources has yielded an optimized device design and a fabrication scheme to implement the design. One major element of the device design is to use a planar array of bundles of carbon nanotubes as the field-emission tips and to optimize the critical dimensions of the array (principally, heights of bundles and distances between them) to obtain high area-averaged current density and high reliability over a long operational lifetime a concept that was discussed in more detail in Arrays of Bundles of Carbon Nanotubes as Field Emitters (NPO-40817), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 58. Another major element of the design is to configure the gate electrodes (anodes used to extract, accelerate, and/or focus electrons) as a ring that overhangs a recess wherein the bundles of nanotubes are located, such that by virtue of the proximity between the ring and the bundles, a relatively low applied potential suffices to generate the large electric field needed for emission of electrons

Method for Manufacturing a Carbon Nanotube Field Emission Device with Overhanging Gate

A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed

Distributed Capacitive Sensor for Sample Mass Measurement

Previous robotic sample return missions lacked in situ sample verification/ quantity measurement instruments. Therefore, the outcome of the mission remained unclear until spacecraft return. In situ sample verification systems such as this Distributed Capacitive (DisC) sensor would enable an unmanned spacecraft system to re-attempt the sample acquisition procedures until the capture of desired sample quantity is positively confirmed, thereby maximizing the prospect for scientific reward. The DisC device contains a 10-cm-diameter pressure-sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in close proximity to an opposing rigid substrate with a narrow gap. The deformation of the membrane makes the gap narrower, resulting in increased capacitance between the two parallel plates (elastic membrane and rigid substrate). C-V conversion circuits on a nearby PCB (printed circuit board) provide capacitance readout via LVDS (low-voltage differential signaling) interface. The capacitance method was chosen over other potential approaches such as the piezoelectric method because of its inherent temperature stability advantage. A reference capacitor and temperature sensor are embedded in the system to compensate for temperature effects. The pressure-sensitive membranes are aluminum 6061, stainless steel (SUS) 403, and metal-coated polyimide plates. The thicknesses of these membranes range from 250 to 500 m. The rigid substrate is made with a 1- to 2-mm-thick wafer of one of the following materials depending on the application requirements glass, silicon, polyimide, PCB substrate. The glass substrate is fabricated by a microelectromechanical systems (MEMS) fabrication approach. Several concentric electrode patterns are printed on the substrate. The initial gap between the two plates, 100 m, is defined by a silicon spacer ring that is anodically bonded to the glass substrate. The fabricated proof-of-concept devices have successfully demonstrated tens to hundreds of picofarads of capacitance change when a simulated sample (100 g to 500 g) is placed on the membrane

Thin Films with Ultra-low Thermal Expansion

Ultra-low coefficient of thermal expansion (CTE) is an elusive property, and narrow temperature ranges of operation and poor mechanical properties limit the use of conventional materials with low CTE. We structured a periodic micro-array of bi-metallic cells to demonstrate ultra-low effective CTE with a wide temperature range. These engineered tunable CTE thin film can be applied to minimize thermal fatigue and failure of optics, semiconductors, biomedical sensors, and solar energy applications

Fabrication Methods for Adaptive Deformable Mirrors

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate

Biblade Sampler

A BiBlade sampler may include a first blade and a second blade in a retracted position. The BiBlade sampler may also include a gripper, which is driven by an actuator. The gripper may include a plurality of fingers to force the first blade and the second blade to remain in a retracted position. When the fingers are unhooked, the first blade and the second blade penetrate a surface of an object

Wafer-To-Wafer Alignment Method

A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented