28 research outputs found

    FPGA Mezzanine Cards for CERN’s Accelerator Control System

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    Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed systems. Initial plans include IO mezzanines for 100Ms/s ADCs and DACs, digital drivers and inputs, high accuracy time tag units and fine delay generators

    The White Rabbit Project

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    Reliable, fast and deterministic transmission of control information in a network is a need formany distributed systems. One example is timing systems, where a reference frequency is used to accurately schedule time-critical messages. TheWhite Rabbit (WR) project is a multi-laboratory and multi-company effort to bring together the best of the data transfer and timing worlds in a completely open design. It takes advantage of the latest developments for improving timing over Ethernet, such as IEEE 1588 (Precision Time Protocol) and Synchronous Ethernet. The presented approach aims for a general purpose, fieldbus-like transmission system, which provides deterministic data and timing (sub-ns accuracy and ps jitter) to around 1000 stations. It automatically compensates for fiber lengths in the order of 10 km. This paper describes the WR design goals and the specification used for the project. It goes on to describe the central component of the WR system structure - the WR switch - with theoretical considerations about the requirements. Finally, it presents real timing measurements for the first prototypes of WR hardware

    Precision measurement of the neutrino velocity with the ICARUS detector in the CNGS beam

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    During May 2012, the CERN-CNGS neutrino beam has been operated for two weeks for a total of 1.8 10^17 pot in bunched mode, with a 3 ns narrow width proton beam bunches, separated by 100 ns. This tightly bunched beam structure allows a very accurate time of flight measurement of neutrinos from CERN to LNGS on an event-by-event basis. Both the ICARUS-T600 PMT-DAQ and the CERN-LNGS timing synchronization have been substantially improved for this campaign, taking ad-vantage of additional independent GPS receivers, both at CERN and LNGS as well as of the deployment of the "White Rabbit" protocol both at CERN and LNGS. The ICARUS-T600 detector has collected 25 beam-associated events; the corresponding time of flight has been accurately evaluated, using all different time synchronization paths. The measured neutrino time of flight is compatible with the arrival of all events with speed equivalent to the one of light: the difference between the expected value based on the speed of light and the measured value is tof_c - tof_nu = (0.10 \pm 0.67stat. \pm 2.39syst.) ns. This result is in agreement with the value previously reported by the ICARUS collaboration, tof_c - tof_nu = (0.3 \pm 4.9stat. \pm 9.0syst.) ns, but with improved statistical and systematic errors.Comment: 21 pages, 13 figures, 1 tabl

    Reliability In A White Rabbit Network

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    White Rabbit (WR) is a time-deterministic, low-latency Ethernet-based network which enables transparent, subns accuracy timing distribution. It is being developed to replace the General Machine Timing (GMT) system currently used at CERN and will become the foundation for the control system of the Facility for Antiproton and Ion Research (FAIR) at GSI. High reliability is an important issue inWR’s design, since unavailability of the accelerator’s control system will directly translate into expensive downtime of the machine. A typical WR network is required to lose not more than a single message per year. Due toWR’s complexity, the translation of this real-world-requirement into a reliability-requirement constitutes an interesting issue on its own – a WR network is considered functional only if it provides all its services to all its clients at any time. This paper defines reliability in WR and describes how it was addressed by dividing it into sub-domains: deterministic packet delivery, data resilience, topology redundancy and clock resilience. The studies show that the Mean Time Between Failure (MTBF) of the WR Network is the main factor affecting its reliability. Therefore, probability calculations for different topologies were performed using the “Fault Tree analysis” and analytic estimations. Results of the study show that the requirements ofWR are demanding. Design changes might be needed and further in-depth studies required, e.g. Monte Carlo simulations. Therefore, a direction for further investigations is proposed

    ZIO: The Ultimate Linux I/O Framework

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    ZIO (with Z standing for “The Ultimate I/O” Framework) was developed for CERN with the specific needs of physics labs in mind, which are poorly addressed in the mainstream Linux kernel. ZIO provides a framework for industrial, high-bandwith, high-channel count I/O device drivers (digitizers, function generators, timing devices like TDCs) with performance, generality and scalability as design goals. Among its features, it offers abstractions for ‱ both input and output channels, and channel sets ‱ run-time selection of trigger types ‱ run-time selection of buffer types ‱ sysfs-based configuration ‱ char devices for data and metadata ‱ a socket interface (PF ZIO) as alternative to char devices In this paper, we discuss the design and implementation of ZIO, and describe representative cases of driver development for typical and exotic applications: drivers for the FMC (FPGAMezzanine Card, see [1]) boards developed at CERN like the FMC ADC 100Msps digitizer, FMC TDC timestamp counter, and FMC DEL fine delay

    CERN's FMC Kit

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    In the context of the renovation of controls and data acquisition electronics for accelerators the BE-CO-HT section at CERN has designed a kit based on carriers and mezzanines following the VITA FPGA Mezzanine Card (FMC) standard

    The White Rabbit project

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    White Rabbit (WR) is a multi-laboratory, multi- company collaboration for the development of a new Ethernet-based technology which ensures sub-nanosecond synchronisation and deterministic data transfer. The project uses an open source paradigm for the development of its hardware, gateware and software components. This article provides an introduction to the technical choices and an explanation of the basic principles underlying WR. It then describes some possible applications and the current status of the project. Finally, it provides insight on current developments and future plans

    White rabbit clock characteristics

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