Electronic architecture for air coupled ultrasonic pulse-echo range finding with application to security and surface profile imaging

Ultrasonic range finding instruments are utilized, e.g., for measuring liquid levels and distance to parking obstacles. However, instruments designed using the conventional electronic architectures to drive the ultrasonic transmitters cannot provide an operating range beyond a few meters for a flat solid wall with normal incidence when powered by a low voltage battery. This both limits the applicability of the existing instruments and makes it difficult to demonstrate their feasibility for new applications. The architecture described here combines a DC/DC boost converter with semiconductor switches, enabling a scalable increase in the operating range for both pulse-echo and pitch-catch modes of operation. It was fully prototyped and successfully tested for novel applications involving ultrasonic range finders, specifically intrusion detection and surface profile imaging. The limitations of the profile sensing device are rather restrictive as it only operates at the incidence angles below 18°, but this device can be developed further. The developed security system was found to be quite practical in its present state

Determining the operating distance of air ultrasound range finders : calculations and experiments

Estimating the operating distance of air ultrasound range finders by using the suitably modified radar equation and experimental verification of the developed computational procedure is discussed. It is shown that, despite notable differences between operating conditions of radars and air ultrasonic range finders, the radar equation is applicable to the considered case, and calculations of the relevant terms for this case are presented. The experimental assessment was carried out by evaluating the probability of detection at various distances from the custom built device. The calculated and experimental results seem to agree well despite using a number of values with high degree of uncertainty. The described procedure can be used at the design stage of air ultrasound range finders in order to reduce the number of prototypes before finalizing the design to a single prototype

Waveform acquisition with resolutions exceeding those of the ADCs employed

This chapter discusses various software/firmware and hardware methods and architectures to improve the fidelity of the acquired waveforms beyond the vertical and horizontal resolutions that are possible with the ADC employed. The applicability of these approaches, and the limits on the enhancements that are achievable, depend upon the nature of the acquired waveform, and they are presented separately for one-shot, repeatable and repetitive waveforms. The possibilities of combining applicable methods in order to simultaneously increase both resolutions are also discussed. The consideration is illustrated by the simulation results and the acquired experimental waveforms relevant to the ultrasonic non-destructive evaluation

Algorithms and Techniques for the Structural Health Monitoring of Bridges: Systematic Literature Review

Structural health monitoring (SHM) systems are used to analyze the health of infrastructures such as bridges, using data from various types of sensors. While SHM systems consist of various stages, feature extraction and pattern recognition steps are the most important. Consequently, signal processing techniques in the feature extraction stage and machine learning algorithms in the pattern recognition stage play an effective role in analyzing the health of bridges. In other words, there exists a plethora of signal processing techniques and machine learning algorithms, and the selection of the appropriate technique/algorithm is guided by the limitations of each technique/algorithm. The selection also depends on the requirements of SHM in terms of damage identification level and operating conditions. This has provided the motivation to conduct a Systematic literature review (SLR) of feature extraction techniques and pattern recognition algorithms for the structural health monitoring of bridges. The existing literature reviews describe the current trends in the field with different focus aspects. However, a systematic literature review that presents an in-depth comparative study of different applications of machine learning algorithms in the field of SHM of bridges does not exist. Furthermore, there is a lack of analytical studies that investigate the SHM systems in terms of several design considerations including feature extraction techniques, analytical approaches (classification/ regression), operational functionality levels (diagnosis/prognosis) and system implementation techniques (data-driven/model-based). Consequently, this paper identifies 45 recent research practices (during 2016–2023), pertaining to feature extraction techniques and pattern recognition algorithms in SHM for bridges through an SLR process. First, the identified research studies are classified into three different categories: supervised learning algorithms, neural networks and a combination of both. Subsequently, an in-depth analysis of various machine learning algorithms is performed in each category. Moreover, the analysis of selected research studies (total = 45) in terms of feature extraction techniques is made, and 25 different techniques are identified. Furthermore, this article also explores other design considerations like analytical approaches in the pattern recognition process, operational functionality and system implementation. It is expected that the outcomes of this research may facilitate the researchers and practitioners of the domain during the selection of appropriate feature extraction techniques, machine learning algorithms and other design considerations according to the SHM system requirements

A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA

This article presents an area-aware unified hardware accelerator of Weierstrass, Edward, and Huff curves over GF(2233) for the point multiplication step in elliptic curve cryptography (ECC). The target implementation platform is a field-programmable gate array (FPGA). In order to explore the design space between processing time and various protection levels, this work employs two different point multiplication algorithms. The first is the Montgomery point multiplication algorithm for the Weierstrass and Edward curves. The second is the Double and Add algorithm for the Binary Huff curve. The area complexity is reduced by efficiently replacing storage elements that result in a 1.93 times decrease in the size of the memory needed. An efficient Karatsuba modular multiplier hardware accelerator is implemented to compute polynomial multiplications. We utilized the square arithmetic unit after the Karatsuba multiplier to execute the quad-block variant of a modular inversion, which preserves lower hardware resources and also reduces clock cycles. Finally, to support three different curves, an efficient controller is implemented. Our unified architecture can operate at a maximum of 294 MHz and utilizes 7423 slices on Virtex-7 FPGA. It takes less computation time than most recent state-of-the-art implementations. Thus, combining different security curves (Weierstrass, Edward, and Huff) in a single design is practical for applications that demand different reliability/security levels

A Hybrid Approach for Efficient and Secure Point Multiplication on Binary Edwards Curves

The focus of this article is to present a novel crypto-accelerator architecture for a resource-constrained embedded system that utilizes elliptic curve cryptography (ECC). The architecture is built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA) attacks. Furthermore, the proposed architecture incorporates several optimizations to achieve efficient hardware resource utilization for the point multiplication process over GF(2m). This includes the use of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed BEC accelerator offers significant performance improvements compared to existing solutions. The obtained throughput over area ratio for GF(2233) on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point multiplication operation on the Virtex-7 device is 19.61 µs. These findings indicate that the proposed architecture has the potential to address the challenges posed by resource-constrained embedded systems that require high throughput and efficient use of available resources

A dynamic framework for internet-based network time protocol

Time synchronization is vital for accurate data collection and processing in sensor networks. Sensors in these networks often operate under fluctuating conditions. However, an accurate timekeeping mechanism is critical even in varying network conditions. Consequently, a synchronization method is required in sensor networks to ensure reliable timekeeping for correlating data accurately across the network. In this research, we present a novel dynamic NTP (Network Time Protocol) algorithm that significantly enhances the precision and reliability of the generalized NTP protocol. It incorporates a dynamic mechanism to determine the Round-Trip Time (RTT), which allows accurate timekeeping even in varying network conditions. The proposed approach has been implemented on an FPGA and a comprehensive performance analysis has been made, comparing three distinct NTP methods: dynamic NTP (DNTP), static NTP (SNTP), and GPS-based NTP (GNTP). As a result, key performance metrics such as variance, standard deviation, mean, and median accuracy have been evaluated. Our findings demonstrate that DNTP is markedly superior in dynamic network scenarios, a common characteristic in sensor networks. This adaptability is important for sensors installed in time-critical networks, such as real-time industrial IoTs, where precise and reliable time synchronization is necessary

Large Field-Size Elliptic Curve Processor for Area-Constrained Applications

This article has proposed an efficient area-optimized elliptic curve cryptographic processor architecture over GF(2409) and GF(2571). The proposed architecture employs Lopez-Dahab projective point arithmetic operations. To do this, a hybrid Karatsuba multiplier of 4-split polynomials is proposed. The proposed multiplier uses general Karatsuba and traditional schoolbook multiplication approaches. Moreover, the multiplier resources are reused to implement the modular squares and addition chains of the Itoh-Tsujii algorithm for inverse computations. The reuse of resources reduces the overall area requirements. The implementation is performed in Verilog (HDL). The achieved results are provided on Xilinx Virtex 7 device. In addition, the performance of the proposed design is evaluated on ASIC 65 nm process technology. Consequently, a figure-of-merit is constructed to compare the FPGA and ASIC implementations. An exhaustive comparison to existing designs in the literature shows that the proposed architecture utilizes less area. Therefore, the proposed design is the right choice for area-constrained cryptographic applications