Bibliometric Review of NoC Router Optimization

Network on chip (NoC) has been proposed as an emerging solution for scalability and performance demands of next generation System on Chip (SoC). NoC provides a solution for the bus based interconnection issue of SoC, where large numbers of Intellectual Property modules (IP) are integrated on a single chip for better performance. The NoC has several advantages such as scalability, low latency and low power consumption, high bandwidth over dedicated wires and buses. Interconnections between multiple chip cores have a significant impact on the communication and performance of the chip design in terms of region, latency, throughput and power. In the NoC architecture, the router is a dominant component that significantly affects the performance of the NoC. NoC router architectures evolved since the year 2002 and progress in the domain pertaining to the optimization in the NoC router architectures has been discussed. The key objective of this bibliometric review is to understand the extent of the existing literature in the domain of performance efficient NoC router architectures. The bibliometric analysis is primarily based on data extracted from Scopus. It reveals that major contributions are done by researchers from USA, China followed by India in the form of conference, journals and articles publications. The major contribution is by the subject areas of Computer Science and Engineering followed by Mathematics and Material Science. The geographical analysis is done by using the GPS visualize tool. The clusters were created using Gephi

A Bibliometric Perspective Survey of IoT controlled AI based Swarm robots

Robotics is the ­new-age domain of technology that deals with bringing a collaboration of all disciplines of sciences and engineering to create a mechanical machine that may or may not work entirely independently but definitely focuses on making human lives much easier. It has repeatedly shown its ability to change lives at home and in the industry. As the field of robotics research grows and reaches new worlds, the military is one area where advances can have a significant impact, and the government is aware of this. Military technology has come a long way from the days where soldiers had to walk into traps, putting their own lives in danger for their fellow soldiers, to today, when soldiers have robots walk into the same traps with possibility and result of zero human casualties. High-risk military operations such as mine detection, bomb defusing, fighter pilot aviation, and entering enemy territory without complete knowledge of what is to come are all tasks that can be programmed in a way that makes them accustomed to scenarios like these, either by intensive machine learning algorithms or artificially intelligent robot systems. Military soldiers are human capital; they are not self-driving robots; they are living beings with emotions, fears, and weaknesses, and they will almost always be unreliable as compared to computers and robots. They are easily affected by environmental effects and are vulnerable to external influences. The government\u27s costs for deployed troops, such as training and salaries, are extremely high. As a result, the solution is to build AI robots for defence operations that can sense, collect data by observing surroundings as any human soldier would, and report it back to a workstation where it can be used for strategy building and planning on what the next step should be during a mission, thus making the army better prepared for any kind of trouble that might be on their way. In this paper, the survey and bibliometric analysis of AI-based IoT managed Swarm Robots from the Scopus repository is discussed, which analyses research by area, notable authors, organizations, funding agencies and countries. Statistical analysis of literature published as journals, articles and papers that aids in understanding the global influence of publication is called Bibliometric analysis. This paper is a thorough analysis of 84 research papers as obtained from the Scopus repository on the 3rd of April 2021. GPS Visualizer, Gephi, wordcloud, and ScienceScape are open source softwares used in the visualization review. As previously mentioned, the visualization assists in a quick and easy interpretation of the different viewpoints in a particular study domain pursuit

Bibliometric Review of NoC Router Optimization

Network on chip (NoC) has been proposed as an emerging solution for scalability and performance demands of next generation System on Chip (SoC). NoC provides a solution for the bus based interconnection issue of SoC, where large numbers of Intellectual Property modules (IP) are integrated on a single chip for better performance. The NoC has several advantages such as scalability, low latency and low power consumption, high bandwidth over dedicated wires and buses. Interconnections between multiple chip cores have a significant impact on the communication and performance of the chip design in terms of region, latency, throughput and power. In the NoC architecture, the router is a dominant component that significantly affects the performance of the NoC. NoC router architectures evolved since the year 2002 and progress in the domain pertaining to the optimization in the NoC router architectures has been discussed. The key objective of this bibliometric review is to understand the extent of the existing literature in the domain of performance efficient NoC router architectures. The bibliometric analysis is primarily based on data extracted from Scopus. It reveals that major contributions are done by researchers from USA, China followed by India in the form of conference, journals and articles publications. The major contribution is by the subject areas of Computer Science and Engineering followed by Mathematics and Material Science. The geographical analysis is done by using the GPS visualize tool. The clusters were created using Gephi

Bibliometric Review of FPGA Based Implementation of CNN

Nowadays Convolution Neural Network (CNN) has become the state of the art for machine learning algorithms due to their high accuracy. However, implementation of CNN algorithms on hardware platforms becomes challenging due to high computation complexity, memory bandwidth and power consumption. Hardware accelerators such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC) are suitable platforms to model CNN algorithms. Recently FPGAs have been considered as an attractive platform for CNN implementation. Modern FPGAs have various embedded hardware and software blocks such as a soft processor, DSP slice and memory blocks. These embedded resources along with customized logic blocks, makes FPGA a perfect candidate for CNN model. Also, the major advantage of FPGA in the case of CNN is its parallelism and pipelining architecture which helps to accelerate CNN operations. The primary goal of this bibliometric review is to determine the scope of current literature in the field of implementing CNN algorithms on various hardware platforms, with a particular emphasis on the FPGA platform for CNN-based applications. Data from Scopus is mostly used in this bibliometric analysis. It reveals that researchers from China, India, and the United Kingdom make the most significant contributions in the form of conferences, journals, and book proceedings. All the documents are from subject areas of Engineering, Computer Science, Mathematics, Physics and Astronomy, Decision Sciences, and Material Science make significant contributions